From 7971426f2462b02ea1bf12d902ca066e07eeb64b Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime@cerno.tech>
Date: Wed, 26 May 2021 16:13:02 +0200
Subject: [PATCH] drm/vc4: Increase the core clock based on HVS load
Depending on a given HVS output (HVS to PixelValves) and input (planes
attached to a channel) load, the HVS needs for the core clock to be
raised above its boot time default.
Failing to do so will result in a vblank timeout and a stalled display
pipeline.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
drivers/gpu/drm/vc4/vc4_kms.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -321,6 +321,7 @@ struct vc4_hvs {
u32 __iomem *dlist;
struct clk *core_clk;
+ struct clk_request *core_req;
/* Memory manager for CRTCs to allocate space in the display
* list. Units are dwords.
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -391,6 +391,11 @@ static void vc4_atomic_commit_tail(struc
new_hvs_state->core_clock_rate);
core_req = clk_request_start(hvs->core_clk, core_rate);
+ /*
+ * And remove the previous one based on the HVS
+ * requirements if any.
+ */
+ clk_request_done(hvs->core_req);
}
drm_atomic_helper_commit_modeset_disables(dev, state);
@@ -418,6 +423,14 @@ static void vc4_atomic_commit_tail(struc
drm_dbg(dev, "Running the core clock at %lu Hz\n",
new_hvs_state->core_clock_rate);
+ /*
+ * Request a clock rate based on the current HVS
+ * requirements.
+ */
+ hvs->core_req = clk_request_start(hvs->core_clk,
+ new_hvs_state->core_clock_rate);
+
+ /* And drop the temporary request */
clk_request_done(core_req);
}
}