From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 21 Oct 2023 13:55:18 +0200 Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock QUP6 I2C clock is listed in the dt bindings but it was never included in the GCC driver. So lets add support for it, it is marked as criticial as it is used by RPM to communicate to the external PMIC over I2C so this clock must not be disabled. Signed-off-by: Robert Marko Reviewed-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -2121,6 +2121,26 @@ static struct clk_branch gcc_blsp1_qup5_ }, }; +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { + .halt_reg = 0x07010, + .clkr = { + .enable_reg = 0x07010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup6_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup6_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + /* + * RPM uses QUP6 I2C to communicate with the external + * PMIC so it must not be disabled. + */ + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .halt_reg = 0x0700c, .clkr = { @@ -4277,6 +4297,7 @@ static struct clk_regmap *gcc_ipq6018_cl [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,