From db7a4a11e8be375b0a9c159f688e0cea49eacc5d Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Thu, 27 Jun 2024 13:04:24 +0200 Subject: [PATCH 2/4] clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC Get rid of prepare and unpreare callbacks for PCIe clock since they can be modeled as a reset line cosumed by the PCIe driver (pcie-mediatek-gen3) Reviewed-by: AngeloGioacchino Del Regno Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/16df149975514d3030499c48fc1c64f090093595.1719485847.git.lorenzo@kernel.org Signed-off-by: Stephen Boyd --- drivers/clk/clk-en7523.c | 41 ++-------------------------------------- 1 file changed, 2 insertions(+), 39 deletions(-) --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -366,9 +366,8 @@ static struct clk_hw *en7523_register_pc cg->base = np_base; cg->hw.init = &init; - if (init.ops->disable) - init.ops->disable(&cg->hw); - init.ops->unprepare(&cg->hw); + if (init.ops->unprepare) + init.ops->unprepare(&cg->hw); if (clk_hw_register(dev, &cg->hw)) return NULL; @@ -386,23 +385,6 @@ static int en7581_pci_is_enabled(struct return (val & mask) == mask; } -static int en7581_pci_prepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - usleep_range(5000, 10000); - - return 0; -} - static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -419,23 +401,6 @@ static int en7581_pci_enable(struct clk_ return 0; } -static void en7581_pci_unprepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val | mask, np_base + REG_RESET_CONTROL1); - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2; - writel(val | mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - msleep(100); -} - static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -656,9 +621,7 @@ static const struct en_clk_soc_data en75 static const struct en_clk_soc_data en7581_data = { .pcie_ops = { .is_enabled = en7581_pci_is_enabled, - .prepare = en7581_pci_prepare, .enable = en7581_pci_enable, - .unprepare = en7581_pci_unprepare, .disable = en7581_pci_disable, }, .reset = {