From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 31 Dec 2022 13:56:26 +0100 Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP table for SoC. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -42,6 +42,7 @@ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@1 { @@ -53,6 +54,7 @@ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@2 { @@ -64,6 +66,7 @@ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@3 { @@ -75,6 +78,7 @@ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache { @@ -84,6 +88,54 @@ }; }; + cpu_opp_table: opp-table { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&cpr_efuse_speedbin>; + opp-shared; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-microvolt = <1>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-microvolt = <2>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-microvolt = <3>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-microvolt = <4>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-microvolt = <5>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <6>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ;