From 542d0f7f2e9f90fc0f02f8cb141f7c3fbf46081b Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 11 Nov 2024 17:11:18 +0000 Subject: [PATCH] dt: rp1: Use clk_sys for ethernet hclk and pclk hclk and pclk of the MAC are connected to clk_sys, so define them as being connected accordingly, rather than having fake fixed clocks for them. Signed-off-by: Dave Stevenson --- arch/arm64/boot/dts/broadcom/rp1.dtsi | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) --- a/arch/arm64/boot/dts/broadcom/rp1.dtsi +++ b/arch/arm64/boot/dts/broadcom/rp1.dtsi @@ -982,7 +982,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&macb_pclk &macb_hclk + clocks = <&rp1_clocks RP1_CLK_SYS + &rp1_clocks RP1_CLK_SYS &rp1_clocks RP1_CLK_ETH_TSU &rp1_clocks RP1_CLK_ETH>; clock-names = "pclk", "hclk", "tsu_clk", "tx_clk"; @@ -1230,18 +1231,6 @@ clock-output-names = "xosc"; clock-frequency = <50000000>; }; - macb_pclk: macb_pclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "pclk"; - clock-frequency = <200000000>; - }; - macb_hclk: macb_hclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "hclk"; - clock-frequency = <200000000>; - }; sdio_src: sdio_src { // 400 MHz on FPGA. PLL sys VCO on asic compatible = "fixed-clock";