#include "mt7620a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc";
	model = "TP-Link Archer C2 v1";

	aliases {
		led-boot = &led_wps;
		led-failsafe = &led_wps;
		led-running = &led_wps;
		led-upgrade = &led_wps;
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	leds {
		compatible = "gpio-leds";

		lan {
			label = "green:lan";
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
		};

		usb {
			label = "green:usb";
			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
			trigger-sources = <&ohci_port1>, <&ehci_port1>;
			linux,default-trigger = "usbport";
		};

		led_wps: wps {
			label = "green:wps";
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};

		wan {
			label = "green:wan";
			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
		};

		wlan {
			label = "green:wlan";
			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy1tpt";
		};
	};

	keys {
		compatible = "gpio-keys";

		reset_wps {
			label = "reset_wps";
			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		rfkill {
			label = "rfkill";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RFKILL>;
		};
	};

	rtl8367rb {
		compatible = "realtek,rtl8367b", "rtl8367b";
		cpu_port = <6>;
		realtek,extif1 = <1 0 1 1 1 1 1 1 2>;
		mii-bus = <&mdio0>;
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <30000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x20000>;
				read-only;
			};

			partition@20000 {
				compatible = "tplink,firmware";
				label = "firmware";
				reg = <0x20000 0x7a0000>;
			};

			partition@7c0000 {
				label = "config";
				reg = <0x7c0000 0x10000>;
				read-only;
			};

			rom: partition@7d0000 {
				label = "rom";
				reg = <0x7d0000 0x10000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					macaddr_rom_f100: macaddr@f100 {
						compatible = "mac-base";
						reg = <0xf100 0x6>;
						#nvmem-cell-cells = <1>;
					};
				};
			};

			partition@7e0000 {
				label = "romfile";
				reg = <0x7e0000 0x10000>;
				read-only;
			};

			radio: partition@7f0000 {
				label = "radio";
				reg = <0x7f0000 0x10000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_radio_0: eeprom@0 {
						reg = <0x0 0x200>;
					};

					eeprom_radio_8000: eeprom@8000 {
						reg = <0x8000 0x200>;
					};
				};
			};
		};
	};
};

&ethernet {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;

	nvmem-cells = <&macaddr_rom_f100 0>;
	nvmem-cell-names = "mac-address";

	port@5 {
		status = "okay";
		mediatek,fixed-link = <1000 1 1 1>;
		phy-mode = "rgmii";
	};

	mdio0: mdio-bus {
		status = "okay";
	};
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&state_default {
	gpio {
		groups = "i2c", "uartf", "wled", "ephy", "spi refclk";
		function = "gpio";
	};
};

&wmac {
	nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>;
	nvmem-cell-names = "eeprom", "mac-address";
};

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&pcie {
	status = "okay";
};

&pcie0 {
	mt76@0,0 {
		reg = <0x0000 0 0 0 0>;
		nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
		nvmem-cell-names = "eeprom", "mac-address";
	};
};