From 1dc069ffadf4ce7817a716f9df2f480254e9b01d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=A3o=20M=C3=A1rio=20Domingos?= Date: Tue, 16 Nov 2021 15:48:10 +0000 Subject: [PATCH 074/116] RISC-V: Support CPUID for risc-v in perf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch creates the header.c file for the risc-v architecture and introduces support for PMU identification through sysfs. It is now possible to configure pmu-events in risc-v. Depends on patch [1], that introduces the id sysfs file. Signed-off-by: João Mário Domingos Signed-off-by: minda.chen --- drivers/perf/riscv_pmu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -18,6 +18,23 @@ #include +PMU_FORMAT_ATTR(event, "config:0-63"); + +static struct attribute *riscv_arch_formats_attr[] = { + &format_attr_event.attr, + NULL, +}; + +static struct attribute_group riscv_pmu_format_group = { + .name = "format", + .attrs = riscv_arch_formats_attr, +}; + +static const struct attribute_group *riscv_pmu_attr_groups[] = { + &riscv_pmu_format_group, + NULL, +}; + static bool riscv_perf_user_access(struct perf_event *event) { return ((event->attr.type == PERF_TYPE_HARDWARE) || @@ -410,6 +427,7 @@ struct riscv_pmu *riscv_pmu_alloc(void) cpuc->events[i] = NULL; } pmu->pmu = (struct pmu) { + .attr_groups = riscv_pmu_attr_groups, .event_init = riscv_pmu_event_init, .event_mapped = riscv_pmu_event_mapped, .event_unmapped = riscv_pmu_event_unmapped,