#include "rt5350.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	compatible = "asiarf,awm002-evb", "ralink,rt5350-soc";

	leds {
		compatible = "gpio-leds";

		tx {
			function = LED_FUNCTION_TX;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
		};

		rx {
			function = LED_FUNCTION_RX;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
		};

		wps {
			function = LED_FUNCTION_WPS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
		};
	};

	keys {
		compatible = "gpio-keys-polled";
		poll-interval = <20>;

		reset_wps {
			label = "reset_wps";
			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		mode {
			label = "mode";
			gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		reg = <0>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x30000>;
				read-only;
			};

			partition@30000 {
				label = "u-boot-env";
				reg = <0x30000 0x10000>;
				read-only;
			};

			factory: partition@40000 {
				label = "factory";
				reg = <0x40000 0x10000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_factory_0: eeprom@0 {
						reg = <0x0 0x200>;
					};

					macaddr_factory_28: macaddr@28 {
						reg = <0x28 0x6>;
					};
				};
			};

			firmware: partition@50000 {
				compatible = "denx,uimage";
				label = "firmware";
				/* reg property is set based on flash size in DTS files */
			};
		};
	};
};

&ethernet {
	nvmem-cells = <&macaddr_factory_28>;
	nvmem-cell-names = "mac-address";
};

&wmac {
	nvmem-cells = <&eeprom_factory_0>;
	nvmem-cell-names = "eeprom";
};

&state_default {
	gpio {
		groups = "i2c", "jtag";
		function = "gpio";
	};
};

&esw {
	mediatek,portmap = <0x3f>;
};