/* * Copyright 2023 SiFlower Corporation. */ #include #include #include #include #include #include / { #address-cells = <2>; #size-cells = <2>; aliases { serial0 = &uart0; serial1 = &uart1; }; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc_svpbmt_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zfh", "zicbom", "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <32768>; i-cache-sets = <128>; d-cache-block-size = <64>; d-cache-size = <32768>; d-cache-sets = <128>; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; clocks = <&topcrm CLK_CPU>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; cpu@1 { compatible = "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc_svpbmt_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zfh", "zicbom", "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <32768>; i-cache-sets = <128>; d-cache-block-size = <64>; d-cache-size = <32768>; d-cache-sets = <128>; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; clocks = <&topcrm CLK_CPU>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; cpu@2 { compatible = "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc_svpbmt_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zfh", "zicbom", "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <32768>; i-cache-sets = <128>; d-cache-block-size = <64>; d-cache-size = <32768>; d-cache-sets = <128>; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; clocks = <&topcrm CLK_CPU>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; cpu@3 { compatible = "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc_svpbmt_zba_zbb_zbc_zbs_zicbom_zicbop_zicboz"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zfh", "zicbom", "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <32768>; i-cache-sets = <128>; d-cache-block-size = <64>; d-cache-size = <32768>; d-cache-sets = <128>; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; clocks = <&topcrm CLK_CPU>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; l2_cache: l2-cache { compatible = "cache"; cache-level = <2>; cache-block-size = <64>; cache-size = <262144>; cache-sets = <256>; cache-unified; }; }; xin25m: xin25m { compatible = "fixed-clock"; clock-output-names = "xin25m"; clock-frequency = <25000000>; #clock-cells = <0>; }; pmu { compatible = "riscv,pmu"; riscv,event-to-mhpmevent = <0x00003 0x0 0x9b>, // L1 Dcache Access <0x00004 0x0 0x9c>, // L1 Dcache Miss <0x00005 0x0 0x36>, // Branch Instruction <0x00006 0x0 0x38>, // Branch Mispred <0x00008 0x0 0x27>, // Stalled Cycles Frontend <0x00009 0x0 0x28>, // Stalled Cycles Backend <0x10000 0x0 0x0c>, // L1-dcache load access <0x10001 0x0 0x0d>, // L1-dcache load miss <0x10002 0x0 0x0e>, // L1-dcache store access <0x10003 0x0 0x0f>, // L1-dcache store miss <0x10004 0x0 0xa2>, // Dcache Hit Caused by Prefetch <0x10005 0x0 0xa1>, // Dcache Refill Caused by Prefetch <0x10008 0x0 0x01>, // L1-icache Access <0x10009 0x0 0x02>, // L1-icache Miss <0x1000c 0x0 0x9e>, // Icache Prefetch <0x1000d 0x0 0xa0>, // Icache Prefetch Miss <0x10010 0x0 0xa5>, // L2 Access <0x10011 0x0 0xa6>, // L2 Miss <0x10019 0x0 0xa4>, // Load Dtlb Miss <0x1001b 0x0 0xa3>, // Store Dtlb Miss <0x10021 0x0 0x03>; // iTLB Miss riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>, // cycles <0x00002 0x00002 0x00000004>, // instructions <0x00003 0x1ffff 0xfffffff8>; // others riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xffffff00 0xfffffff8>; }; timer: timer { compatible = "riscv,timer"; }; reset: reset-controller { compatible = "siflower,sf21-reset"; #reset-cells = <1>; siflower,crm = <&topcrm>; }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; dma-noncoherent; ranges; interrupt-parent = <&plic>; pcie0: pcie@00200000 { compatible = "siflower,sf21-pcie"; status = "disabled"; reg = <0x0 0x00000000 0x0 0x200000>, <0x0 0x00200000 0x0 0x100000>, <0x0 0x00300000 0x0 0x080000>, <0x0 0x00380000 0x0 0x080000>, <0x0 0xa0000000 0x0 0x080000>; reg-names = "dbi", "elbi", "atu", "dma", "config"; clocks = <&topcrm CLK_SERDES_CSR>, <&topcrm CLK_PCIE_REFP>, <&topcrm CLK_PCIEPLL_FOUT3>; clock-names = "csr", "ref", "phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0xa0080000 0x0 0xa0080000 0x0 0x00080000 /* downstream I/O 256KB */ 0x82000000 0x0 0xa0100000 0x0 0xa0100000 0x0 0x2ff00000>; /* non-prefetchable memory */ siflower,ctlr-idx = <0>; num-viewport = <8>; interrupts = <124 IRQ_TYPE_LEVEL_HIGH>, <160 IRQ_TYPE_LEVEL_HIGH>, <161 IRQ_TYPE_LEVEL_HIGH>, <162 IRQ_TYPE_LEVEL_HIGH>, <163 IRQ_TYPE_LEVEL_HIGH>, <164 IRQ_TYPE_LEVEL_HIGH>, <165 IRQ_TYPE_LEVEL_HIGH>, <166 IRQ_TYPE_LEVEL_HIGH>, <167 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "intr", "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &plic 151 IRQ_TYPE_EDGE_RISING>, <0 0 0 2 &plic 150 IRQ_TYPE_EDGE_RISING>, <0 0 0 3 &plic 149 IRQ_TYPE_EDGE_RISING>, <0 0 0 4 &plic 148 IRQ_TYPE_EDGE_RISING>; siflower,pcie-sysm = <&pcie_phy>; phys = <&pcie_phy0>; linux,pci-domain = <0>; }; pcie1: pcie@04200000 { compatible = "siflower,sf21-pcie"; status = "disabled"; reg = <0x0 0x04000000 0x0 0x200000>, <0x0 0x04200000 0x0 0x100000>, <0x0 0x04300000 0x0 0x080000>, <0x0 0x04380000 0x0 0x080000>, <0x0 0xd0000000 0x0 0x080000>; reg-names = "dbi", "elbi", "atu", "dma", "config"; clocks = <&topcrm CLK_SERDES_CSR>, <&topcrm CLK_PCIE_REFP>, <&topcrm CLK_PCIEPLL_FOUT3>; clock-names = "csr", "ref", "phy"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0xd0080000 0x0 0xd0080000 0x0 0x00080000 /* downstream I/O 256KB */ 0x82000000 0x0 0xd0100000 0x0 0xd0100000 0x0 0x2ff00000>; /* non-prefetchable memory */ siflower,ctlr-idx = <1>; num-viewport = <8>; interrupts = <125 IRQ_TYPE_LEVEL_HIGH>, <168 IRQ_TYPE_LEVEL_HIGH>, <169 IRQ_TYPE_LEVEL_HIGH>, <170 IRQ_TYPE_LEVEL_HIGH>, <171 IRQ_TYPE_LEVEL_HIGH>, <172 IRQ_TYPE_LEVEL_HIGH>, <173 IRQ_TYPE_LEVEL_HIGH>, <174 IRQ_TYPE_LEVEL_HIGH>, <175 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "intr", "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &plic 159 IRQ_TYPE_EDGE_RISING>, <0 0 0 2 &plic 158 IRQ_TYPE_EDGE_RISING>, <0 0 0 3 &plic 157 IRQ_TYPE_EDGE_RISING>, <0 0 0 4 &plic 156 IRQ_TYPE_EDGE_RISING>; siflower,pcie-sysm = <&pcie_phy>; phys = <&pcie_phy1>; linux,pci-domain = <1>; }; topcrm: clock-controller@0ce00400 { compatible = "siflower,sf21-topcrm", "syscon"; reg = <0x0 0x0ce00400 0x0 0x400>; clocks = <&xin25m>; clock-names = "xin25m"; #clock-cells = <1>; }; i2crst: reset-controller@0ce08400 { compatible = "siflower,sf19a2890-periph-reset"; reg = <0x0 0x0ce08400 0x0 0x4>; #reset-cells = <1>; siflower,num-resets = <2>; }; i2cclk: clock-controller@0ce08404 { compatible = "siflower,sf19a2890-periph-clk"; reg = <0x0 0x0ce08404 0x0 0x4>; clocks = <&topcrm CLK_APB>, <&topcrm CLK_APB>; clock-output-names = "i2c0", "i2c1"; #clock-cells = <1>; }; spirst: reset-controller@0ce08800 { compatible = "siflower,sf19a2890-periph-reset"; reg = <0x0 0x0ce08800 0x0 0x4>; #reset-cells = <1>; siflower,reset-masks = <0x3 0xc>; }; spiclk: clock-controller@0ce08804 { compatible = "siflower,sf19a2890-periph-clk"; reg = <0x0 0x0ce08804 0x0 0x4>; clocks = <&topcrm CLK_APB>, <&topcrm CLK_APB>, <&topcrm CLK_APB>, <&topcrm CLK_APB>; clock-output-names = "spi0_apb", "spi0_ssp", "spi1_apb", "spi1_ssp"; #clock-cells = <1>; }; uartrst: reset-controller@0ce08c00 { compatible = "siflower,sf19a2890-periph-reset"; reg = <0x0 0x0ce08c00 0x0 0x4>; #reset-cells = <1>; siflower,reset-masks = <0x11 0x22>; }; uartclk: clock-controller@0ce08c04 { compatible = "siflower,sf19a2890-periph-clk"; reg = <0x0 0x0ce08c04 0x0 0x4>; clocks = <&topcrm CLK_APB>, <&topcrm CLK_APB>, <&topcrm CLK_UART>, <&topcrm CLK_UART>; clock-output-names = "uart0_apb", "uart1_apb", "uart0", "uart1"; siflower,valid-gates = <0x33>; siflower,critical-gates = <0x22>; #clock-cells = <1>; }; timerst: reset-controller@0ce09800 { compatible = "siflower,sf19a2890-periph-reset"; reg = <0x0 0x0ce09800 0x0 0x4>; #reset-cells = <1>; siflower,reset-masks = <0x1>; }; timerclk: clock-controller@0ce09804 { compatible = "siflower,sf19a2890-periph-clk"; reg = <0x0 0x0ce09804 0x0 0x4>; clocks = <&topcrm CLK_APB>; clock-output-names = "timer"; #clock-cells = <1>; }; wdtrst: reset-controller@0ce09c00 { compatible = "siflower,sf19a2890-periph-reset"; reg = <0x0 0x0ce09c00 0x0 0x4>; #reset-cells = <1>; siflower,reset-masks = <0x1>; }; wdtclk: clock-controller@0ce09c04 { compatible = "siflower,sf19a2890-periph-clk"; reg = <0x0 0x0ce09c04 0x0 0x4>; clocks = <&topcrm CLK_APB>; clock-output-names = "wdt"; #clock-cells = <1>; }; gpiorst: reset-controller@0ce0a000 { compatible = "siflower,sf19a2890-periph-reset"; reg = <0x0 0x0ce0a000 0x0 0x4>; #reset-cells = <1>; siflower,reset-masks = <0x1>; }; gpioclk: clock-controller@0ce0a004 { compatible = "siflower,sf19a2890-periph-clk"; reg = <0x0 0x0ce0a004 0x0 0x4>; clocks = <&topcrm CLK_APB>; clock-output-names = "gpio"; #clock-cells = <1>; }; uart0: uart@c300000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; clocks = <&uartclk 2>, <&uartclk 0>; clock-names = "uartclk", "apb_pclk"; resets = <&uartrst 0>; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; current-speed = <115200>; status = "disabled"; }; uart1: uart@c301000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xc301000 0x0 0x1000>; clocks = <&uartclk 3>, <&uartclk 1>; clock-names = "uartclk", "apb_pclk"; resets = <&uartrst 1>; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; current-speed = <115200>; status = "disabled"; }; spi0: spi@c200000 { compatible = "siflower,sf21-qspi"; reg = <0x0 0xc200000 0x0 0x1000>; clocks = <&spiclk 0>, <&spiclk 1>; clock-names = "apb_pclk", "sspclk"; resets = <&spirst 0>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@c201000 { compatible = "siflower,sf21-qspi"; reg = <0x0 0xc201000 0x0 0x1000>; clocks = <&spiclk 2>, <&spiclk 3>; clock-names = "apb_pclk", "sspclk"; resets = <&spirst 1>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; watchdog: watchdog@0c700000 { compatible = "snps,dw-wdt"; reg = <0x0 0x0c700000 0x0 0x1000>; interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wdtclk 0>; resets = <&wdtrst 0>; }; usb_phy: phy@0ce02400 { compatible = "siflower,sf21-usb-phy"; reg = <0x0 0x0ce02400 0x0 0x14>; clocks = <&topcrm CLK_USBPHY>; clock-names = "usb_phy_clk"; #phy-cells = <0>; status = "disabled"; }; pcie_phy: phy@0d810000 { compatible = "siflower,sf21-pcie-phy", "syscon"; reg = <0x0 0x0d810000 0x0 0x100>; clocks = <&topcrm CLK_PCIE_REFP>, <&topcrm CLK_SERDES_CSR>; clock-names = "ref", "csr"; siflower,topcrm = <&topcrm>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; pcie_phy0: phy@0 { reg = <0>; siflower,num-lanes = <1>; #phy-cells = <0>; }; pcie_phy1: phy@1 { reg = <1>; siflower,num-lanes = <1>; #phy-cells = <0>; }; }; usb: usb@10000000 { compatible = "siflower,sf19a2890-usb"; reg = <0x0 0x10000000 0x0 0x80000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topcrm CLK_USB>; clock-names = "otg"; resets = <&reset SF21_RESET_USB>; reset-names = "dwc2"; dr_mode = "host"; phys = <&usb_phy>; phy-names = "usb2-phy"; g-rx-fifo-size = <512>; g-np-tx-fifo-size = <128>; g-tx-fifo-size = <128 128 128 128 128 128 128 128 16 16 16 16 16 16 16>; status = "disabled"; }; iram: sram@1c000000 { compatible = "mmio-sram"; reg = <0x0 0x1c000000 0x0 0x10000>; clocks = <&topcrm CLK_IRAM>; ranges; }; xgmac0: ethernet@8000000 { compatible = "siflower,sf21-xgmac"; reg = <0x0 0x8000000 0x0 0x4000>; dmas = <&edma>; ethsys = <ðsys>; clocks = <&topcrm CLK_SERDES_CSR>; clock-names = "csr"; pcs-handle = <&qsgmii_pcs 0>; phy-mode = "qsgmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_mdio_pins>; interrupts = <176 IRQ_TYPE_LEVEL_HIGH>, <20 IRQ_TYPE_LEVEL_HIGH>, <26 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sbd", "lpi", "pmt"; status = "disabled"; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; }; }; xgmac1: ethernet@8004000 { compatible = "siflower,sf21-xgmac"; reg = <0x0 0x8004000 0x0 0x4000>; dmas = <&edma>; ethsys = <ðsys>; clocks = <&topcrm CLK_SERDES_CSR>; clock-names = "csr"; pcs-handle = <&qsgmii_pcs 1>; phy-mode = "qsgmii"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, <21 IRQ_TYPE_LEVEL_HIGH>, <27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sbd", "lpi", "pmt"; status = "disabled"; }; xgmac2: ethernet@8008000 { compatible = "siflower,sf21-xgmac"; reg = <0x0 0x8008000 0x0 0x4000>; dmas = <&edma>; ethsys = <ðsys>; clocks = <&topcrm CLK_SERDES_CSR>; clock-names = "csr"; pcs-handle = <&qsgmii_pcs 2>; phy-mode = "qsgmii"; interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, <22 IRQ_TYPE_LEVEL_HIGH>, <28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sbd", "lpi", "pmt"; status = "disabled"; }; xgmac3: ethernet@800c000 { compatible = "siflower,sf21-xgmac"; reg = <0x0 0x800c000 0x0 0x4000>; dmas = <&edma>; ethsys = <ðsys>; clocks = <&topcrm CLK_SERDES_CSR>; clock-names = "csr"; pcs-handle = <&qsgmii_pcs 3>; phy-mode = "qsgmii"; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <23 IRQ_TYPE_LEVEL_HIGH>, <29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sbd", "lpi", "pmt"; status = "disabled"; }; xgmac4: ethernet@8010000 { compatible = "siflower,sf21-xgmac"; reg = <0x0 0x8010000 0x0 0x4000>; dmas = <&edma>; ethsys = <ðsys>; clocks = <&topcrm CLK_SERDES_CSR>; clock-names = "csr"; pcs-handle = <&sgmii_pcs 0>; phy-mode = "2500base-x"; pinctrl-names = "default"; pinctrl-0 = <&mac4_mdio_pins>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, <24 IRQ_TYPE_LEVEL_HIGH>, <30 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sbd", "lpi", "pmt"; status = "disabled"; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; }; }; edma: dma-controller@8018000 { compatible = "siflower,sf21-xgmac-dma"; reg = <0x0 0x8018000 0x0 0x4000>; #dma-cells = <0>; ethsys = <ðsys>; iram = <&iram>; clocks = <&topcrm CLK_AXI>, <&topcrm CLK_NPU>, <&topcrm CLK_SERDES_CSR>; clock-names = "axi", "npu", "csr"; interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <9 IRQ_TYPE_LEVEL_HIGH>, <10 IRQ_TYPE_LEVEL_HIGH>, <11 IRQ_TYPE_LEVEL_HIGH>, <12 IRQ_TYPE_LEVEL_HIGH>, <13 IRQ_TYPE_LEVEL_HIGH>, <14 IRQ_TYPE_LEVEL_HIGH>, <15 IRQ_TYPE_LEVEL_HIGH>, <16 IRQ_TYPE_LEVEL_HIGH>, <17 IRQ_TYPE_LEVEL_HIGH>, <18 IRQ_TYPE_LEVEL_HIGH>, <19 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sbd", "tx0", "tx1", "tx2", "tx3", "tx4", "rx0", "rx1", "rx2", "rx3", "rx4", "rxovf"; status = "disabled"; }; qsgmii_pcs: xpcs@8800000 { compatible = "siflower,sf21-xpcs"; reg = <0x0 0x8800000 0x0 0x800000>; ethsys = <ðsys>; clocks = <&topcrm CLK_ETH_REF_P>, <&topcrm CLK_ETHTSU>, <&topcrm CLK_SERDES_CSR>; clock-names = "ref", "eee", "csr"; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sgmii_pcs: xpcs@9000000 { compatible = "siflower,sf21-xpcs"; reg = <0x0 0x9000000 0x0 0x800000>; ethsys = <ðsys>; clocks = <&topcrm CLK_ETH_REF_P>, <&topcrm CLK_ETHTSU>, <&topcrm CLK_SERDES_CSR>; clock-names = "ref", "eee", "csr"; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; gpio: gpio@c800000 { compatible = "siflower,sf19a2890-gpio"; reg = <0x0 0xc800000 0x0 0x100000>; gpio-controller; #gpio-cells = <2>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, <55 IRQ_TYPE_LEVEL_HIGH>, <56 IRQ_TYPE_LEVEL_HIGH>, <57 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&gpioclk 0>; resets = <&gpiorst 0>; ngpios = <41>; gpio-ranges = <&iomux 0 0 41>; }; i2c0: i2c@c100000 { compatible = "snps,designware-i2c"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&i2cclk 0>; clock-names = "ref"; clock-frequency = <400000>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names="default"; pinctrl-0 = <&i2c0_pins>; resets = <&i2crst 0>; status = "disabled"; }; i2c1: i2c@c101000 { compatible = "snps,designware-i2c"; reg = <0x0 0xc101000 0x0 0x1000>; clocks = <&i2cclk 1>; clock-frequency = <400000>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; ethsys: syscon@ce01800 { compatible = "siflower,ethsys", "syscon"; reg = <0x0 0xce01800 0x0 0x800>; }; dpns: dpns@11000000 { compatible = "siflower,sf21-dpns"; reg = <0x0 0x11000000 0x0 0x1000000>; #address-cells = <1>; dma-ranges = <0 0x0 0 0x20000000 0 0x80000000>; interrupts = <65 IRQ_TYPE_EDGE_RISING>, <66 IRQ_TYPE_EDGE_RISING>, <67 IRQ_TYPE_EDGE_RISING>, <68 IRQ_TYPE_EDGE_RISING>, <69 IRQ_TYPE_EDGE_RISING>, <70 IRQ_TYPE_EDGE_RISING>, <71 IRQ_TYPE_EDGE_RISING>, <72 IRQ_TYPE_EDGE_RISING>, <73 IRQ_TYPE_EDGE_RISING>, <74 IRQ_TYPE_EDGE_RISING>, <75 IRQ_TYPE_EDGE_RISING>, <76 IRQ_TYPE_EDGE_RISING>, <77 IRQ_TYPE_EDGE_RISING>, <78 IRQ_TYPE_EDGE_RISING>, <79 IRQ_TYPE_EDGE_RISING>, <80 IRQ_TYPE_EDGE_RISING>, <81 IRQ_TYPE_EDGE_RISING>, <82 IRQ_TYPE_EDGE_RISING>, <83 IRQ_TYPE_EDGE_RISING>, <84 IRQ_TYPE_EDGE_RISING>, <85 IRQ_TYPE_LEVEL_HIGH>, <86 IRQ_TYPE_LEVEL_HIGH>, <87 IRQ_TYPE_EDGE_RISING>, <88 IRQ_TYPE_EDGE_RISING>, <89 IRQ_TYPE_EDGE_RISING>, <90 IRQ_TYPE_EDGE_RISING>, <91 IRQ_TYPE_EDGE_RISING>, <92 IRQ_TYPE_EDGE_RISING>, <93 IRQ_TYPE_EDGE_RISING>, <94 IRQ_TYPE_EDGE_RISING>, <95 IRQ_TYPE_EDGE_RISING>, <96 IRQ_TYPE_EDGE_RISING>, <97 IRQ_TYPE_EDGE_RISING>, <98 IRQ_TYPE_EDGE_RISING>, <99 IRQ_TYPE_EDGE_RISING>, <100 IRQ_TYPE_EDGE_RISING>, <101 IRQ_TYPE_EDGE_RISING>, <102 IRQ_TYPE_EDGE_RISING>, <103 IRQ_TYPE_EDGE_RISING>, <104 IRQ_TYPE_EDGE_RISING>, <105 IRQ_TYPE_EDGE_RISING>, <106 IRQ_TYPE_EDGE_RISING>, <107 IRQ_TYPE_EDGE_RISING>, <108 IRQ_TYPE_EDGE_RISING>, <109 IRQ_TYPE_EDGE_RISING>, <110 IRQ_TYPE_EDGE_RISING>, <111 IRQ_TYPE_EDGE_RISING>, <112 IRQ_TYPE_EDGE_RISING>, <113 IRQ_TYPE_EDGE_RISING>, <114 IRQ_TYPE_EDGE_RISING>, <115 IRQ_TYPE_EDGE_RISING>, <116 IRQ_TYPE_EDGE_RISING>, <117 IRQ_TYPE_EDGE_RISING>, <118 IRQ_TYPE_EDGE_RISING>, <119 IRQ_TYPE_EDGE_RISING>, <120 IRQ_TYPE_EDGE_RISING>, <121 IRQ_TYPE_EDGE_RISING>, <122 IRQ_TYPE_EDGE_RISING>; ethsys = <ðsys>; clocks = <&topcrm CLK_NPU>; resets = <&reset SF21_RESET_NPU>, <&reset SF21_RESET_NPU2DDR_ASYNCBRIDGE>; reset-names = "npu", "npu2ddr"; siflower,edma = <&edma>; status = "disabled"; }; syscon@ce00000 { compatible = "siflower,brom-sysm"; reg = <0x0 0xce00000 0x0 0x400>; #reset-cells = <1>; }; syscon@ce00c00 { compatible = "siflower,cpu-sysm"; reg = <0x0 0xce00c00 0x0 0x400>; }; iomux: iomux@ce3c000 { compatible = "pinconf-single"; reg = <0x0 0xce3c000 0x0 0xa4>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = ; pinctrl-single,function-off = <0>; pinctrl-single,gpio-range = <&range 0 41 GPIO_MODE>; range: gpio-range { #pinctrl-single,gpio-range-cells = <3>; }; clk_pins: clk_pins { pinctrl-single,pins = < EXT_CLK_IN FUNC_MODE0 CLK_OUT FUNC_MODE0 >; }; spi0_pins: spi0_pins { pinctrl-single,pins = < SPI0_TXD FUNC_MODE0 SPI0_RXD FUNC_MODE0 SPI0_CLK FUNC_MODE0 SPI0_CSN FUNC_MODE0 SPI0_HOLD FUNC_MODE0 SPI0_WP FUNC_MODE0 >; }; jtag_pins: jtag_pins { pinctrl-single,pins = < JTAG_TDO FUNC_MODE0 JTAG_TDI FUNC_MODE0 JTAG_TMS FUNC_MODE0 JTAG_TCK FUNC_MODE0 JTAG_RST FUNC_MODE0 >; }; uart0_pins: uart0_pins { pinctrl-single,pins = < JTAG_TDO FUNC_MODE1 JTAG_TDI FUNC_MODE1 JTAG_TMS FUNC_MODE1 JTAG_TCK FUNC_MODE1 >; }; uart1_pins: uart1_pins { pinctrl-single,pins = < UART1_TX FUNC_MODE0 UART1_RX FUNC_MODE0 >; }; uart1_full_pins: uart1_full_pins { pinctrl-single,pins = < UART1_TX FUNC_MODE0 UART1_RX FUNC_MODE0 I2C0_DAT FUNC_MODE1 I2C0_CLK FUNC_MODE1 >; }; i2c0_pins: i2c0_pins { pinctrl-single,pins = < I2C0_DAT FUNC_MODE0 I2C0_CLK FUNC_MODE0 >; }; perst_pins: perst_pins { pinctrl-single,pins = < I2C0_DAT FUNC_MODE2 I2C0_CLK FUNC_MODE2 >; }; i2c1_pins: i2c1_pins { pinctrl-single,pins = < I2C1_DAT FUNC_MODE0 I2C1_CLK FUNC_MODE0 >; }; rgmii_pins: rgmii_pins { pinctrl-single,pins = < RGMII_GTX_CLK FUNC_MODE0 RGMII_TXD0 FUNC_MODE0 RGMII_TXD1 FUNC_MODE0 RGMII_TXD2 FUNC_MODE0 RGMII_TXD3 FUNC_MODE0 RGMII_TXCTL FUNC_MODE0 RGMII_RXCLK FUNC_MODE0 RGMII_RXD0 FUNC_MODE0 RGMII_RXD1 FUNC_MODE0 RGMII_RXD2 FUNC_MODE0 RGMII_RXD3 FUNC_MODE0 RGMII_RXCTL FUNC_MODE0 >; }; spi1_pins: spi1_pins { pinctrl-single,pins = < RGMII_GTX_CLK FUNC_MODE1 RGMII_TXCLK FUNC_MODE1 RGMII_TXD0 FUNC_MODE1 RGMII_TXD1 FUNC_MODE1 RGMII_TXD2 FUNC_MODE1 RGMII_TXD3 FUNC_MODE1 >; }; mac0_mdio_pins: mac0_mdio_pins { pinctrl-single,pins = < QSGMII_MDIO FUNC_MODE0 QSGMII_MDC FUNC_MODE0 >; }; mac4_mdio_pins: mac4_mdio_pins { pinctrl-single,pins = < SXGMII_MDIO FUNC_MODE0 SXGMII_MDC FUNC_MODE0 >; }; }; plic: interrupt-controller@108000000 { compatible = "thead,c900-plic"; reg = <0x1 0x8000000 0x0 0x400000>, <0x0 0x0ce00c34 0x0 0x20>; interrupt-controller; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu3_intc 11>, <&cpu3_intc 9>; #interrupt-cells = <2>; riscv,ndev = <176>; }; interrupt-controller@10c000000 { compatible = "thead,c900-aclint-mswi"; reg = <0x1 0xc000000 0x0 0x4000>; interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>, <&cpu2_intc 3>, <&cpu3_intc 3>; }; timer@10c004000 { compatible = "thead,c900-aclint-mtimer"; reg = <0x1 0xc00bff8 0x0 0x8>, <0x1 0xc004000 0x0 0x7ff8>; interrupts-extended = <&cpu0_intc 7>, <&cpu1_intc 7>, <&cpu2_intc 7>, <&cpu3_intc 7>; }; interrupt-controller@10c00c000 { compatible = "thead,c900-aclint-sswi"; reg = <0x1 0xc00c000 0x0 0x1000>; interrupts-extended = <&cpu0_intc 1>, <&cpu1_intc 1>, <&cpu2_intc 1>, <&cpu3_intc 1>; }; }; };