According to the Realtek SDK code, the RTL8214FC, RTL8218B and RTL8218FB
all have the same chip ID 0x6276. Let's add a constant for it, as we're
using it in more than one location.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Respect the phy-is-integrated property on ethernet-phy nodes.
There are RTL8393M switches where the PHYs at address 48 and 49 are
provided by an external RTL8214FC. Hardcoding them to use the internal
SerDes makes it impossible to use the ports connected to such an
external PHY. Respect the phy-is-integrated property on ethernet-phy
nodes as a first step to support such ports.
The potential impact for this should be limited to RTL8393 based
switches, and looking at the commit messages and device tree files of
the supported switches based on this SoC, the SFP and/or combo ports are
either not working (D-Link DGS-1210-52, Netgear GS750E, TP-Link
SG2452P/T1600G-52PS), use PHYs at a different address (Panasonic
SwitchM48EG PN28480K), or already have the phy-is-integrated property
set on the PHYs at address 48 and 49.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Daniel Golle <daniel@makrotopia.org>
The function introduced in commit 7cbfe5654d is named
filter_port_list_reverse, not filter_port_list_reversed.
Fixes the following error on hpe,1920-8g-poe-65w and
hpe,1920-8g-poe-180w.
/bin/board_detect: /etc/board.d/02_network: line 84: filter_port_list_reversed: not found
Fixes: 7cbfe5654d ("realtek: move port filtering out of uci_set_poe()")
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Sander Vanheule <sander@svanheule.net>
This device is very similar to the GS1900-24E switch (added in b515ad1),
except that the first 12 of 24 ethernet ports are capable of PoE and the
physical jacks are in the right order - unlike for the GS1900-24E, where
even and uneven ports are flipped (up <-> down on panel).
Zyxel version code for this device (-24EP) is: ABTO
Signed-off-by: Mirko Vogt <mirko-openwrt@nanl.de>
The Zyxel GS1900-8 v2 or Rev.B1 is a newer variant of the GS1900-8, but
otherwise similar to the other GS1900 switches.
Differences
------------
* Front Button labeled RESTORE
* NO Power Switch on rear
* Serial Header next to the barrel power connector
* Part Number ends 0102F
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
D-Link DGS-1210-16 hangs when rebooting and has no support for the reset
button.
Fix both by enabling the same GPIOs for reboot and the reset button as
already used for D-Link DGS-1210-20 and D-Link DGS-1210-28.
Signed-off-by: Richard Kunze <kunze@tivano.de>
Recent OEM firmware versions test the version number embedded in the uimage
"name" header field. The exact restricton is unknown, but "7.0.8.4" seems
to be the lowest number accepted on a GS110TPPv1 which already has that
version or higher.
A "9.9.9.9" version is accepted as valid by the GS110TPPv1 OEM firmware,
and considered both unique enough to identify an OpenWrt image and
moderately future proof against OEM version bumps.
This change is also boot tested on a GS108Tv3 with
"BOOT Loader Version 1.0.0.2 (2018-08-31 17:05:26 UTC)"
to verify that it doesn't break boot on older hardware.
Link: https://forum.openwrt.org/t/72510/58
Signed-off-by: Bjørn Mork <bjorn@mork.no>
PoE devices in the realtek target have the possibility to add PSE info
to the board description via 02_network. Make this available for all
targets, by moving the uci_set_poe() function to the globally available
uci-default.sh script.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
uci_set_poe() now performs two duties: filtering the list of device
ports to exclude non-PoE ports, and generating the PoE related device
config.
Extract the port filtering to an external function, which is made a bit
more readable by the use of 'sort -V [-r] | uniq -u' to filter duplicate
entries out of a (reverse) version sorted list.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The ZyXEL XGS1250-12 has a chassis fan. The fan is positioned perfectly to
provide additional cooling to the Aquantia NBase-T phys. Testing has shown
that the phys can reach temperatures upwards of 72 degrees Celsius quite
easily at about 20 degrees Celsius ambient.
Support the chassis fan to give the phys a bit of extra cooling.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
Initial conversion to new LED color/function format
and drop label format where possible. The same label
is composed at runtime.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Drop redundant label with new LED color/function format declared.
This was needed previously when the new format wasn't supported by
leds.sh functions script. Now that is supported this property
can be removed in favor of the new format.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The rtl93xx SoC supports both 1000Base-X and 10GBase-CR on its SerDes
interfaces. Enable dynamic switching between mac-signaled modes to
support 1000Base-X and 10GBase-CR on the SFP port.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch adds support for 1000Base-X and 10GBase-CR directly on the
SerDes lanes of rtl93xx SoCs.
This fixes SFP/SFP+ support on devices like the XSG1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
Commit daefc646e6 ("realtek: fix ZyXEL initramfs image generation")
fixed a shell expansion issue with zyxel-vers usage. Commit 045baca10b
("realtek: deduplicate GS1900 recipes") took care of this for the
rtl838x and rtl839x subtargets, but the single device officially
supported in rtl930x - the XGS1250-12 - was overlooked. This commit
updates the XGS1250-12 build recipe as well.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Backport merged upstream patch that adds support for firmware loader
from NVMEM or attached filesystem for Aquantia PHYs.
Refresh all kernel patches affected by this change.
Also update the path for aquantia .ko that got moved to dedicated
directory upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
[rmilecki: port to 5.15]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Refresh HSGMII patch due to recent PHY backport that cause
compilation warning for case not handled in phy_interface_num_ports.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The current dts file of dgs-1210-10p doesn't support link states
for the sfp ports (they are always up).
This patch tries to give better support for this and was run tested
on dgs-1210-10p.
It was heavily inspired from Paul Fertser, RaylynnKnight
and the author of dgs-1210-10mp-f.dts
https://forum.openwrt.org/t/dlink-dgs-1210-10p-with-glc-t-co-sfp/170928
Signed-off-by: Michel Thill <jmthill@gmail.com>
The register constants were duplicated in net/dsa/rtl83xx/debugfs.c and asm
mach-rtl838x/mach-rtl83xx.h. This commit removes this duplication.
Signed-off-by: Peter Körner <git@mazdermind.de>
According to https://svanheule.net/realtek/maple/register/led_sw_ctrl and also
drivers/net/dsa/rtl83xx/debugfs.c LED_SW_CTRL on the RTL838X should be 0xa00c
not 0x0128. Please note, that is is 0x0128 on the RTL8390/cypress SOC family.
Signed-off-by: Peter Körner <git@mazdermind.de>
the given code-format did not correctly express the condition and made the code
harder to read then necessary.
Signed-off-by: Peter Körner <git@mazdermind.de>
The GS110TUP v1 is a managed switch similar to the GS110TPP v1, but with
port 10 as SFP instead of RJ-45 and a total budget of 240 watts. Ports
1-4 support 60-watt 802.3bt PoE and ports 5-8 support 30-watt 802.3at.
The flash layout of the two switches are identical, and the U-Boot
configurations are the same except for having a different magic number,
so installation can be done via the same U-Boot method.
The following command will be needed to enable the port LEDs as per
https://forum.openwrt.org/t/72510/51 :
fw_setenv bootcmd "rtk network on; boota"
Additionally, port 9 (1000base-T from a separate QSGMII PHY) does not
function without this. Port 10 was not tested as no SFP module was
available.
Signed-off-by: Jacob Potter <jacob@j4cbo.com>
[rebase on merged flash layout]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.
Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before, PVID is reset for all ports and goes out of bounds. Also, PVID
is later changed by dsa configuration by `ip link` and `bridge vlan`
commands, this does not change the CPU port PVID and CPU PVID stays 0.
It does not allow sending packets from OpenWrt to any connected devices
unless default configuration is changed
This change iterates up to and including cpu_port and sets default PVID
to 1. For lan* ports PVID can be configured with `ip link` and `bridge
vlan` commands
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Fix incorrect register value being set for VLAN_PORT_FWD
Before, the 0b1111 would be set for the register which means outgoing
packets would receive an extra tag, corresponding to the PVID of the
port.
On untagged ports, this meant outgoing packets with a single tag.
On tagged ports, this meant outgoing QinQ packets, where the inner tag
was either the PVID of the untagged ingress port, or the already
assigned original (single) tag.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Without this, luci shows 10M full duplex when there is no link. So
explicitly set half duplex and unknown speed.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Use led_setX to determine number of LEDs per port. Introduce macros to
calculate register value and shift for particular LED in a particular
set.
Problem with previous implementation is that it uses is10G status to
determine leds per port. However with usxgmii, driver sets 10g, 5g and
2.5g so even though there are only 2 leds per port it selects 4 leds per
port
This implementation relies on configured led_set node.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Before driver code
- enabled egress filter for cpu and non-cpu ports
- enabled ingress filter for non-cpu ports
This patch explicitly enables ingress and egress filtering for non-cpu
ports and disables ingress and egress filtering for cpu port.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Currently OpenWRT does not know how to properly reset the network switch. This would result in
a switch that seemed to come up properly but was unable to handle any traffic. Presumably something
earlier in the boot chain is configuring a part of the switch that gets wiped out when its reset.
For now comment out the reset GPIO entry in the device tree until the driver better supports
bringing up the switch after a reset.
Signed-off-by: Michael 'ASAP' Weinrich <michael@a5ap.net>
The upper 16 bits of the 32 bit value encode the SoC model in BCD
notation (for example 0x83806800 on a Netgear GS108Tv3 with an
RTL8380M), so it makes more sense to output the value in hex notation
than in decimal notation.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
The MAC embedded in rtl93xx switch SoCs needs different mac mode bits set
to support 10BaseT and 100BaseT link modes. Set them accordingly.
This change has been tested on a ZyXEL XGS1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch cleans up and standardizes realtek-poe support for realtek
based switches that have supported PoE ports.
The power output of switches supported by realtek-poe package can be
configured in the 02_network ucidef_set_poe() function. This was missed
when some PoE capable switches supported by realtek-poe were added.
The realtek-poe package at one point replaced a lua-rs232 based script
and some devices were not updated to use the realtek-poe package.
Consistently add realtek-poe package to DEVICE_PACKAGES for switches
with supported PoE.
Signed-off-by: Raylynn Knight <rayknight@me.com>
This is an RTL8382-based switch with 24 copper ports + 4 SFP ports
Specifications:
---------------
* SoC: Realtek RTL8382M
* Flash: 32 MiB SPI flash
* RAM: 256 MiB
* Ethernet: 24x 10/100/1000 Mbps
* Buttons: 1x "Reset" button
* UART: 1x serial header, unpopulated
* SFP: 4 SFP ports
Works:
------
- (24) RJ-45 ethernet ports
- Switch functions
- Buttons
- Sys LED on front panel (no port LEDs)
Not yet enabled:
----------------
- Port LEDs (no driver for RTL8231 in this mode)
- SFP cages (no driver for PHY)
Install via web interface:
-------------------------
Not supported at this time.
Install via serial console/tftp:
--------------------------------
The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U6)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as soon as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWRT.
Blind install via tftp:
-----------------------
This method works when it's not feasible to install a serial header.
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
3. Watch network traffic (tcpdump or wireshark works)
4. Power on the device.
5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
6. When 192.168.0.30 makes tftp requests, release pin 16
7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Hardware information:
---------------------
- RTL8380 SoC
- 8 Gigabit RJ45 PoE ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
- PoE chip
- Fanless
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '65'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
There are two hardware models of the HPE 1920-8g-poe switch. The version
currently in the repository is the model with a PoE budget of 180W. In
preparation of the addition of the 65W model, the existing model is
renamed to clarify the hardware version it targets.
As suggested by Pawel, the 'SUPPORTED_DEVICES' includes the old target
name to enable an upgrade path of builds with the old name.
Suggested-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
Fix Spanning Tree Protocol (STP) by changing COPY2CPU which currently
makes switch to ignore Bridge Protocol Data Units (BPDUs).
Tested on Zyxel GS1900-8, 24 and 48.
Signed-off-by: Rudolf Vesely <i@rudolfvesely.com>
[ improve commit description and add new line in different sections ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
