2 Commits

Author	SHA1	Message	Date
Michael Pratt	290a6527be	ath79: add pcie1 wifi device to Senao qca955x AP DTSI ... Each individual device DTS now enables either pcie0 or pcie1. Signed-off-by: Michael Pratt <mcpratt@pm.me>	2023-01-28 20:34:00 +01:00
Michael Pratt	41be1a2de2	ath79: add support for Araknis AN-700-AP-I-AC ... FCC ID: 2AG6R-AN700APIAC Araknis AN-700-AP-I-AC is an indoor wireless access point with 1 Gb ethernet port, dual-band wireless, internal antenna plates, and 802.3at PoE+ this board is a Senao device: the hardware is equivalent to EnGenius EAP1750 the software is modified Senao SDK which is based on openwrt and uboot including image checksum verification at boot time, and a failsafe image that boots if checksum fails **Specification:** - QCA9558 SOC MIPS 74kc, 2.4 GHz WMAC, 3x3 - QCA9880 WLAN PCI card, 5 GHz, 3x3, 26dBm - AR8035-A PHY RGMII GbE with PoE+ IN - 40 MHz clock - 16 MB FLASH MX25L12845EMI-10G - 2x 64 MB RAM NT5TU32M16 - UART console J10, populated, RX shorted to ground - 4 antennas 5 dBi, internal omni-directional plates - 4 LEDs power, 2G, 5G, wps - 1 button reset NOTE: all 4 gpio controlled LEDS are viewed through the same lightguide therefore, the power LED is off for default state **MAC addresses:** MAC address labeled as ETH Only one Vendor MAC address in flash at art 0x0 eth0 ETH *:xb art 0x0 phy1 2.4G *:xc --- phy0 5GHz *:xd --- **Serial Access:** the RX line on the board for UART is shorted to ground by resistor R176 therefore it must be removed to use the console but it is not necessary to remove to view boot log optionally, R175 can be replaced with a solder bridge short the resistors R175 and R176 are next to the UART RX pin at J10 **Installation:** Method 1: Firmware upgrade page: (if you cannot access the APs webpage) factory reset with the reset button connect ethernet to a computer OEM webpage at 192.168.20.253 username and password 'araknis' make a new password, login again... Navigate to 'File Management' page from left pane Click Browse and select the factory.bin image Upload and verify checksum Click Continue to confirm wait about 3 minutes Method 2: Serial to load Failsafe webpage: After connecting to serial console and rebooting... Interrupt uboot with any key pressed rapidly execute `run failsafe_boot` OR `bootm 0x9fd70000` wait a minute connect to ethernet and navigate to 192.168.20.253 Select the factory.bin image and upload wait about 3 minutes **Return to OEM:** Method 1: Serial to load Failsafe webpage (above) Method 2: delete a checksum from uboot-env this will make uboot load the failsafe image at next boot because it will fail the checksum verification of the image ssh into openwrt and run `fw_setenv rootfs_checksum 0` reboot, wait a minute connect to ethernet and navigate to 192.168.20.253 select OEM firmware image and click upgrade Method 3: backup mtd partitions before upgrade **TFTP recovery:** Requires serial console, reset button does nothing rename initramfs-kernel.bin to '0101A8C0.img' make available on TFTP server at 192.168.1.101 power board, interrupt boot with serial console execute `tftpboot` and `bootm 0x81000000` NOTE: TFTP may not be reliable due to bugged bootloader set MTU to 600 and try many times **Format of OEM firmware image:** The OEM software is built using SDKs from Senao which is based on a heavily modified version of Openwrt Kamikaze or Altitude Adjustment. One of the many modifications is sysupgrade being performed by a custom script. Images are verified through successful unpackaging, correct filenames and size requirements for both kernel and rootfs files, and that they start with the correct magic numbers (first 2 bytes) for the respective headers. Newer Senao software requires more checks but their script includes a way to skip them. The OEM upgrade script is at /etc/fwupgrade.sh OKLI kernel loader is required because the OEM software expects the kernel to be less than 1536k and the OEM upgrade procedure would otherwise overwrite part of the kernel when writing rootfs. Note on PLL-data cells: The default PLL register values will not work because of the external AR8035 switch between the SOC and the ethernet port. For QCA955x series, the PLL registers for eth0 and eth1 can be see in the DTSI as 0x28 and 0x48 respectively. Therefore the PLL registers can be read from uboot for each link speed after attempting tftpboot or another network action using that link speed with `md 0x18050028 1` and `md 0x18050048 1`. The clock delay required for RGMII can be applied at the PHY side, using the at803x driver `phy-mode` setting through the DTS. Therefore, the Ethernet Configuration registers for GMAC0 do not need the bits for RGMII delay on the MAC side. This is possible due to fixes in at803x driver since Linux 5.1 and 5.3 Signed-off-by: Michael Pratt <mcpratt@pm.me>	2022-03-13 19:54:58 +01:00