XHCI bus numbers are assigned dynamically, it may varies among boards,
match the device irq name with regexp, drop the hardcoded name.
Signed-off-by: Furong Xu <xfr@outlook.com>
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
identical to OrangePi R1 Plus.
Tested-by: Volkan Yetik <no3iverson@gmail.com>
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
This device is similar to the NanoPi R2S, and has a 16MB
SPI NOR (mx25l12805d). The reset button is changed to
directly reset the power supply, another detail is that
both network ports have independent MAC addresses.
Note: booting from SPI is currently unsupported, you have to install
the image on a SD card.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
On the NanoPI R4S it takes an average of 3..5 seconds for the network devices
to appear in '/proc/interrupts'.
Wait up to 10 seconds to ensure that the distribution of the interrupts
really happens.
Signed-off-by: Ronny Kotzschmar <ro.ok@me.com>
Hardware
--------
RockChip RK3399 ARM64 (6 cores)
4GB LPDDR4 RAM
2x 1000 Base-T
3 LEDs (LAN / WAN / SYS)
1 Button (Reset)
Micro-SD slot
2x USB 3.0 Port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card using
dd.
=====================================
NOTICE FOR USERS WHO USE 1GB VERSION:
BY NOW IT IS NOT SUPPORTED
====================================
[initialed target]
Co-developed-by: Marty Jones <mj8263788@gmail.com>
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[fixed bootscript]
Co-developed-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This adds a hotplug script for distributing interrupts of eth0 and eth1
across different cores. Otherwise the forwarding performance between
eth0 and eth1 is severely affected.
The existing SMP distribution mechanic in OpenWrt can't be used here, as
the actual device IRQ has to be moved to dedicated cores. In case of
eth1, this is in fact the USB3 controller.
Signed-off-by: David Bauer <mail@david-bauer.net>
