This device seems to have switch port 7 connected to the CPU:
vlan1ports=1 2 3 5 7*
vlan2ports=0 7u
it should be handled by eth1 and NVRAM seems to confirm that (no
et0macaddr entry, existing et1macaddr & et1phyaddr entries).
One of the remaining ports (4/8?) may be connected to the Quantenna SoC.
Original firmware boot log contains following messages:
(0x00,0x5d)Port 5 States Override: 0xfb
(0x00,0x5f)Port 7 States Override: 0xfb
(0x00,0x0e)Port 8 States Override: 0x0a
(why does it force port 5 state?!)
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45692
It has 3 Ethernet interfaces, each of them connected to separated switch
port. Default NVRAM uses switch port 8 as CPU which is connected to the
3rd interface (eth2).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45681
It seems to have few ports connected to CPU (only for CPU sending data?)
as part of "SMP dual core 3 GMAC setup" feature.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45403
This new argument is used right after starting regular preinit (which
happens if failsafe wasn't triggered). The main purpose of "preinit"
argument is to indicate that failsafe can be triggered, however we were
missing a way to inform user that we don't wait for a trigger anymore.
With this change it's clear when failsafe mode can be triggered.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 43715
Without running fixtrx the image will not boot at the second time,
because the CRC the boot loader check is invalid at that time.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 42639
