Commit Graph

19 Commits

Author SHA1 Message Date
Martin Blumenstingl
d76ee5bfac lantiq: specify the PCIe controller's interrupt, size and address cells
This allows adding devices to the PCIe controller in the .dts files.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
2016-11-26 22:39:27 +01:00
Mathias Kresin
2b55c83e68 treewide: dts: use keycode defines from input dt-binding
All compiled device tree files not mentioned are binary identical to the
former ones.

Fix the obvious decimal/hex confusion for the power key of ramips/M2M.dts.

Due to the include of the input binding header, the BTN_* node names in:

  - ramips/GL-MT300A.dts
  - ramips/GL-MT300N.dts
  - ramips/GL-MT750.dts
  - ramips/Timecloud.dts

will be changed by the compiler to the numerical equivalent.

Move the binding include of lantiq boards to the file where they are
used the first time to hint the user where the values do come from.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-11-13 07:07:58 +01:00
Mathias Kresin
112cf52d45 lantiq: cleanup dts files
- remove not existing properties
- remove properties having the same values as the included dtsi
- remove nodes which are disabled in the included dtsi and not enabled
  in dts
- replace the deprecated pinctrl-* compatible strings
- use the same labels for nodes as the included dtsi
- move common used vr9 pci properties to vr9.dtsi
- remove the unused stp node from HomeHub 2B devcie tree source file
- fix spaces vs. tabs and remove superfluous linebreaks

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-11-03 19:00:28 +01:00
Stefan Koch
01ab5209c0 lantiq: modify vr9.dts to support vmmc
(required not-distributable firmware blob - dump it by yourself from original firmware)

Signed-off-by: Eddi De Pieri <eddi@depieri.net>

(cherry picked from commit 8d924d43c0ea6839a3a33e54982e8da48b736001)

Modified after cherry-pick:
compatible attribute

Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
2016-10-31 16:51:32 +01:00
Mathias Kresin
3c5a8a2cbc lantiq: enable cpu temp driver for all vr9 boards
Only present on v1.2 vr9 SoCs but the driver takes care to not load on
boards having a v1.1 SoC.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-10-19 19:55:06 +02:00
Andreas Eberlein
eba84bee4c lantiq: Sanitize device tree files
The device tree file of ARV752DPW uses numbers/hex values for gpio states and input event codes.

This cleans it up and uses the available macros from header files. This way the functions are easier to read and comprehend.

Signed-off-by: Andreas Eberlein <foodeas@aeberlein.de>
[sanitize all device tree files]
Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-10-19 19:55:04 +02:00
Martin Schiller
ddd1882811 lantiq/xrx200-net: add interrupt for second DMA TX channel to vr9.dtsi
Signed-off-by: Martin Schiller <mschiller@tdt.de>
2016-08-15 15:32:36 +02:00
John Crispin
b50b0cff2d lantiq: use new property name for eiu irqs
Signed-off-by: John Crispin <john@phrozen.org>
2016-06-13 22:51:41 +02:00
Felix Fietkau
022855baf2 lantiq: Move the definition of the xrx200-net node to vr9.dtsi
This removes a lot of duplicate register and interrupt definitions by
moving the xrx200-net definition to vr9.dtsi and making all devices re-
use it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48547
2016-01-29 00:42:45 +00:00
Felix Fietkau
04ad02d132 lantiq: Switch to the new SPI driver
Compared to the "old" driver:
- Each device must assign a pinctrl setting to the SPI node to allow the
  new SPI driver to configure the SPI pins.
  While here we are also using separate input and output settings so we
  are independent of whether the bootloader configures the pins correctly.
- We use the new "compatible" strings to make the driver choose the
  correct number of chip-selects for each SoC.
- The new driver starts counting the chip-selects at 1 (instead of 0, like
  the old one did). Thus we have to adjust the devices accordingly.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48293
2016-01-17 19:56:03 +00:00
Felix Fietkau
a5c177943b lantiq: Add the SPI node to ar9.dtsi and vr9.dtsi
This allows devices to use SPI without having to re-define (and thus
duplicating) the whole SPI node.
By default SPI is disabled (as before) because only few devices need it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48286
2016-01-17 19:55:17 +00:00
Felix Fietkau
3f8a426056 lantiq: Configure the PCIe reset GPIO using OF
After the latest pinctrl backports there are only 50 (instead of 56 as
before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now
462, before it was 456). This means that any hardcoded GPIOs have to be
adjusted.
This broke the PCIe driver (which seems to be the only driver which uses
hardcoded GPIO numbers), it only reports:
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	pcie_rc_initialize link up failed!!!!!

To prevent more of these issues in the future we remove the hardcoded
PCIe reset GPIO definition and simply pass it via device-tree (like the
PCI driver does).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48285
2016-01-17 19:55:10 +00:00
Felix Fietkau
1204a1b1e5 lantiq: Use the new pinctrl compatible strings
These were introduced in upstream commit
be14811c03cf "pinctrl/lantiq: introduce new dedicated devicetree
bindings" and finally allow us to use the individual pins within our dts
(for example spi_clk, etc.).
Please note that this changes the number of GPIOs which are available for
some SoCs. VRX200 SoCs for example only have 50 pins, but previously 56
pins were exposed. This means that all places which are using hardcoded
GPIO numbers (which are not passed via device-tree) need to be adjusted
(because the first GPIO number is now 462, instead of 456).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48284
2016-01-17 19:55:04 +00:00
John Crispin
8c80e915a0 lantiq: Add the xbar to vr9.dts
linux 4.4 (since commit 08b3c894e56580b8ed3e601212a25bda974c3cc2
"MIPS: lantiq: Disable xbar fpi burst mode") requires that the xbar is
defined in the .dts of vrx200 (VR9) SoCs.

SVN-Revision: 48056
2016-01-01 21:21:00 +00:00
John Crispin
415fe71d00 lantiq: Make the MEI address available for kernel drivers
Newer DSL driver versions depend on the address information.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 46221
2015-07-07 13:44:32 +00:00
John Crispin
2a390925df lantiq: Convert Zyxel P-2812HNU-FX and TP-Link TD-W8970 to support dwc2
Here the device tree entry for ifxhcd is listed as compatible with one
supported in dwc2 (after patching the dwc driver appropriately).

A second entry is added to support the second core of the hcd. This
entry is listed to be compatible with only dwc2. Done this way there
should be backwards support for both hcd drivers (ltq-hcd and dwc2)

Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>

SVN-Revision: 44676
2015-03-11 17:08:32 +00:00
John Crispin
826b461427 lantiq: add 3.18 support
Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 44348
2015-02-09 12:13:25 +00:00
Luka Perkov
da7590cd21 lantiq: fix formating in .dts files
Signed-off-by: Luka Perkov <luka@openwrt.org>

SVN-Revision: 36882
2013-06-08 11:36:07 +00:00
John Crispin
157c86371f lantiq: move dts files to thir own folder
Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 36443
2013-04-25 19:03:32 +00:00