Add support for Xilinx ZC702 Dev board
Zynq target is using 4.4 kernel and mainline 2016.1 u-boot.
Patch is tested with Xilinx ZC702 Dev board with SD boot mode.
known issues:
- no QSPI driver in 4.4 kernel: no QSPI flash support
- USB is not working in 4.4 kernel
Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
create mode 100644 package/boot/uboot-zynq/Makefile
create mode 100644 target/linux/zynq/Makefile
create mode 100644 target/linux/zynq/base-files.mk
create mode 100755 target/linux/zynq/base-files/etc/board.d/02_network
create mode 100644 target/linux/zynq/base-files/etc/config/network
create mode 100644 target/linux/zynq/base-files/etc/inittab
create mode 100644 target/linux/zynq/config-4.4
create mode 100644 target/linux/zynq/image/Makefile
create mode 100755 target/linux/zynq/image/mkits.sh
create mode 100644 target/linux/zynq/patches-4.4/0001-arm-dts-zynq-zc702.dts-Set-default-rdinit-to-sbin-in.patch
create mode 100644 target/linux/zynq/profiles/zc702.mk
SVN-Revision: 48697
Many gpio controllers 'cansleep' due to the fact that they are behind busses
e.g. i2c etc.
Using threaded irq's allows for 'sleep-able' gpio's to be used.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 48696
This reverts r48591, users needing NFS root will know how to configure
their platform and kernel command-line appropriately.
Reported-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 48689
Seama header has MD5 similarly to TRX and its CRC32. We need to update
it after replacing anything in Seama entity content to make bootloader
accept it.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48688
Update OpenWRT build tree to reflect changes in TLC-591xx LED family driver.
In kernels < 4.0 the driver was present in form of a patch for the TLC-59116 chip,
and was upstreamed later in kernels > 4.0 to support the entire chip family.
Signed-off-by: Sebastian Careba <nitroshift@yahoo.com>
[jow: fix Kconfig symbol name]
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 48684
With this patch sysupgrade will write directly to the partitions
instead of to the main disk. The UUID is copied from the image
to the MBR as well. This prevents the mbr from being completely
overwritten and losing the partition table. The -p option has
been added to maintain the original behavior and overwite the
entire disk with the new image. Tests have been added to ensure
that the image partitions match up with the active partitions.
Signed-off-by: Rob Mosher <nyt-openwrt@countercultured.net>
SVN-Revision: 48682
It was enabled ages ago when it was added.
It still saves about 10k after LZMA, so let's enable it again.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48680
Add a new variable TARGET_INIT_PATH which holds the default $PATH variable
value configured in menuconfig.
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 48676
The top half of UARTF on the HLK-RM04 is used for GPIO.
mode 1 mode 2
RIN GPIO14
DSR_N GPIO13
DCD_N GPIO12
DTR_N GPIO11
RXD GPIO10
CTS_N GPIO09
TXD GPIO08
RTS_N GPIO07
This patch applies 3'b101 mode to UARTF:
GPIO14
GPIO13
GPIO12
GPIO11
RXD
CTS_N
TXD
RTS_N
Because the base rt5350.dtsi file forces 3'b000 mode, remove the pin setting from this file and apply it directly to the files that inherit from it (WIZFI630A.dts and WT1520.dtsi). This change makes the rt5350.dtsi file consistent with the mt7620a.dtsi file.
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48665
The I2C function of the RT5350 SoC on the HLK-RM04 is used for GPIO1 and GPIO2.
Take note that the I2C_SD pin is GPIO1 on the RT5350 and is exposed on the HLK-RM04 as GPIO0
Likewise the I2C_SCLK pin is GPIO2 on the RT5350 and is exposed on the HLK-RM04 as GPIO1
group mode 1 mode 2 hlk-rm04 pin & export
i2c i2c_sd gpio1 (pin 8, hlk-rm04:gpio0)
i2c i2c_sclk gpio2 (pin 9, hlk-rm04:gpio1)
reference:
http://www.hlktech.net/product_detail.php?ProId=39http://cdn.sparkfun.com/datasheets/Wireless/WiFi/RT5350.pdf
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48664
The RESET button of the HLK-RM04 is connected to GPIO0, linux function 0x198
The WPS button of the HLK-RM04 is connected to GPIO14, linux function 0x211
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48663
The power LED on the HLK-RM04 is hard wired to the power bus and is not under GPIO control, remove the bogus config for it.
(Note that GPIO0 is actually connected to the RESET button.)
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48662
On systems that have an RTC prefer it to the file-based time fixup (i.e.
use hwclock when there is a permanent clock instead of the faked up time
logic that is needed when there is not RTC).
We can't rely on hctosys kernel feature either as we're usually using
RTC as kernel modules which are usually being loaded after hctosys was
run, leading in the following error:
hctosys: unable to open rtc device (rtc0)
Signed-off-by: Daniel Dickinson <openwrt@daniel.thecshore.com>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
SVN-Revision: 48661
With the backport of the kernel 4.5 pinctrl-xway patches (3551609d &
826bca29) the pinmux group "spi" was splitted into "spi_di", "spi_do" &
"spi_clk". But the no longer existing group "spi" is still used by some
device tree source files.
This fixes the detection of the wireless chipset of the VGV7510KW22.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 48658
The stock u-boot doesn't disable unused flash banks. Therefore, the nand
driver tries to initialize a not connected NOR flash and the device
hangs on boot.
Workaround the issue by selecting the second flash bank (NAND).
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48657
