The top half of UARTF on the HLK-RM04 is used for GPIO.
mode 1 mode 2
RIN GPIO14
DSR_N GPIO13
DCD_N GPIO12
DTR_N GPIO11
RXD GPIO10
CTS_N GPIO09
TXD GPIO08
RTS_N GPIO07
This patch applies 3'b101 mode to UARTF:
GPIO14
GPIO13
GPIO12
GPIO11
RXD
CTS_N
TXD
RTS_N
Because the base rt5350.dtsi file forces 3'b000 mode, remove the pin setting from this file and apply it directly to the files that inherit from it (WIZFI630A.dts and WT1520.dtsi). This change makes the rt5350.dtsi file consistent with the mt7620a.dtsi file.
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48665
The I2C function of the RT5350 SoC on the HLK-RM04 is used for GPIO1 and GPIO2.
Take note that the I2C_SD pin is GPIO1 on the RT5350 and is exposed on the HLK-RM04 as GPIO0
Likewise the I2C_SCLK pin is GPIO2 on the RT5350 and is exposed on the HLK-RM04 as GPIO1
group mode 1 mode 2 hlk-rm04 pin & export
i2c i2c_sd gpio1 (pin 8, hlk-rm04:gpio0)
i2c i2c_sclk gpio2 (pin 9, hlk-rm04:gpio1)
reference:
http://www.hlktech.net/product_detail.php?ProId=39http://cdn.sparkfun.com/datasheets/Wireless/WiFi/RT5350.pdf
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48664
The RESET button of the HLK-RM04 is connected to GPIO0, linux function 0x198
The WPS button of the HLK-RM04 is connected to GPIO14, linux function 0x211
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48663
The power LED on the HLK-RM04 is hard wired to the power bus and is not under GPIO control, remove the bogus config for it.
(Note that GPIO0 is actually connected to the RESET button.)
Signed-off-by: John Clark <inindev@gmail.com>
SVN-Revision: 48662
With the backport of the kernel 4.5 pinctrl-xway patches (3551609d &
826bca29) the pinmux group "spi" was splitted into "spi_di", "spi_do" &
"spi_clk". But the no longer existing group "spi" is still used by some
device tree source files.
This fixes the detection of the wireless chipset of the VGV7510KW22.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 48658
The stock u-boot doesn't disable unused flash banks. Therefore, the nand
driver tries to initialize a not connected NOR flash and the device
hangs on boot.
Workaround the issue by selecting the second flash bank (NAND).
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48657
When dealing with Broadcom hardware we can simply use swconfig's generic
helper, we just need to do some validation of requested state.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48623
Thanks to this change swconfig can access port PHYs e.g. when setting
port link state with a generic helper.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48622
It's quite common for switches to have PHY per port so adding a generic
helper setting link state will help many drivers. It just needs an API
to access PHYs which this patch also adds.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48621
Some D-Link routers (e.g. DIR-885L) have NAND and use Seama format. It
means OpenWrt will want to have UBI in Sseama entity and should be able
to detect it.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48600
Our mtdsplit parsers may want to create partition with name choice based
on partition file system (e.g. SquashFS vs. JFFS2). This patch allows
passing extra argument pointing to variable that will be set properly.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 48598
All other SoC types are using "lantiq,sram" and "simple-bus" to ensure
that all child nodes are set up correctly during linux kernel
initialization (plat_of_setup(void) in arch/mips/lantiq/prom.c). Without
this some of sram child nodes might not be parsed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48548
This removes a lot of duplicate register and interrupt definitions by
moving the xrx200-net definition to vr9.dtsi and making all devices re-
use it.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48547
