Commit Graph

8 Commits

Author SHA1 Message Date
Adrian Schmutzler
84fc80dd66 rockchip: remove useless echo in 40-net-smp-affinity
The command in the $() brackets will already provide the same output.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-08-17 23:13:57 +02:00
Hauke Mehrtens
b35c54227b kernel: Move CONFIG_IONIC to generic kernel config
It is deactivated everywhere, just set this in the generic config.

Acked-by: Yousong Zhou <yszhou4tech@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2020-08-10 23:58:58 +02:00
David Bauer
c5360894dc rockchip: enable rockchip-thermal
Enable the rockchip-thermal driver to allow reading the temperature of
the SoC.

Tested on NanoPi R2S

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-07-29 01:40:20 +02:00
David Bauer
7a4fc8906c rockchip: distribute net interrupts
This adds a hotplug script for distributing interrupts of eth0 and eth1
across different cores. Otherwise the forwarding performance between
eth0 and eth1 is severely affected.

The existing SMP distribution mechanic in OpenWrt can't be used here, as
the actual device IRQ has to be moved to dedicated cores. In case of
eth1, this is in fact the USB3 controller.

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-07-28 15:52:44 +02:00
David Bauer
b7a9a183fb rockchip: add NanoPi R2S support
Hardware
--------
RockChip RK3328 ARM64 (4 cores)
1GB DDR4 RAM
2x 1000 Base-T
3 LEDs (LAN / WAN / SYS)
1 Button (Reset)
Micro-SD slot
USB 2.0 Port

Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card using
dd.

MAC-address
-----------
The vendor code supports reading a MAC address from an EEPROM connected
via i2c0 of the SoC. The EEPROM (address 0x51) should contain the MAC
address in binary at offset 0xfa. However, my two units didn't come with
such an EEPROM soldered on. The EEPROM should be placed between the SoC
and the GPIO pins on the board. (U10)

Generating rendom MAC addresses works around this issue. Otherwise, all
boards running the same image have identical MAC addresses.

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-07-28 15:52:44 +02:00
David Bauer
0485fb3925 rockchip: don't disable timer LED trigger
The timer LED trigger is enabled in all targets (except for lantiq
xway-legacy). It's necessary for the OpenWrt preinit LED pattern to
work.

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-07-13 17:50:53 +02:00
David Bauer
875a04478c rockchip: use downstream GPIO button implementation
Use the OpenWrt netlink GPIO button implementation to forward button
presses to procd. This is necessary to make failsafe-mode access
using a button possible.

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-07-13 17:50:35 +02:00
Tobias Mädel
6a05a85dcb rockchip: add support for Pine64 RockPro64
This adds the new rockchip target and support for RockPro64 RK3399

Flash:    16 MiB SPI NOR
RAM:      2 GiB/4 GiB LPDDR4
SoC:      RK3399
USB:      2x USB 2.0, 1x USB 3.0, 1x USB-C
Ethernet: 1x GbE
PCIe:     PCIe 2.0, 4 lanes
Storage:  eMMC or SD card
Optional SDIO wifi/bt module

The Pine64 RockPro64 is a single-board-computer with a 4x PCIe connector,
6 ARM64 cores (4 little, 2 big), plenty of RAM and storage.

By default the single Gigabit-Ethernet port is configured as the
LAN port.

Installation of the firware is possible by dd'ing the image
to an SD card or the eMMC flash.

Serial: 3v3 1500000 8n1

U-boot is build from the mainline tree and
integrated into the images. Required ATF to build u-boot
is downloaded from a CI build bot.

Signed-off-by: Tobias Mädel <t.maedel@alfeld.de>
Tested-by: Tobias Schramm <t.schramm@manjaro.org>
2020-04-20 16:37:56 +02:00