This patch ports the cybertan_part code from ar71xx and converts the
driver to a DT-supported mtd parser. As a result, it will no longer
add the u-boot, nvram and art partitions, which were never part of
the special Cybertan header.
Instead these partitions have to be specified in the DT, which has the
upside of making it possible to add properties (i.e.: read-only), labels
and references to these important partitions.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Without "syscon" being present in an ag71xx ethernet DT node's
compatible property, a panic occurs at boot during probe citing
"Unhandled kernel unaligned access".
With this modification, the panic no longer occurs and instead the probe
simply fails, allowing the boot process to continue.
Signed-off-by: Matt Merhar <mattmerhar@protonmail.com>
We currently don't have any code configuring interface mode in ath79,
meaning that we relies on bootloader to set the correct interface mode.
This patch added code to set interface correctly so that everything works
even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set
the second GMAC mode to RMII but it should be RGMII.)
Introduced "qca,mac-idx" for the difference in MII_CTRL register value.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET
in datasheets will trigger either a reset for builtin switch or assert
an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected
to external PHY/switch. None of them should be triggered every time an
interface is brought up in ethernet driver.
Remove PHY reset support from ag71xx and definition for them in dtsi.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
mdio bus isn't a standalone device on ar7240. (and maybe older SoCs?)
Use simple-mfd for ar7241 and later SoCs to get mdio1 ready before gmac0
For ar7240 and older chips, manually create platform device after
ag71xx_hw_init() in ag71xx_probe()to get mdio0 ready between
ag71xx_hw_init() and ag71xx_phy_connect().
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Allow specifying desired mdio clock frequency in dts.
Use default frequency around 5MHz for builtin switch and 2MHz for other mdio bus.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This patch did several things:
1. Probe the builtin switch as a separated mdio device.
2. Register a separated mdio bus for builtin switch.
3. Use generic mdio read/write function instead of calling ag71xx_mdio_mii_read/write directly.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
We need to have mdio1 belonging to gmac1 initialized before gmac0.
Split it into a separated mdio device to get both mdios ready before probing gmac.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
The builtin switch has it's initial valid mac address(00:00:01:00:00:00).
Since the builtin switch is an independent device, setting mac address of gmac1 to builtin switch isn't a good idea and this makes it impossilbe to split builtin switch apart as an independent platform device.
Remove these functions and apply default VLAN during initialization as a preparation for further driver splitting.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Due do a missing KCONFIG isn't selectable nor enabled in the target
kernel config. Drop it for now and enable/add the driver at the time it
is required.
Signed-off-by: Mathias Kresin <dev@kresin.me>
ar71xx/ar913x series use the old pll registers and settings.
However started from ar7242, a new pll register is introduced and the
pll setting is much simpler.
This can be observed from dev-eth.c from the ar71xx target.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
1. compatible property in node gmac was wrong
2. ag71xx_setup_gmac_933x should use np of gmac-config and
not the pointer to gmac. gmac is only used for the reg address.
Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.
Signed-off-by: John Crispin <john@phrozen.org>
