Commit Graph

3 Commits

Author SHA1 Message Date
Hannu Nyman
91add68e50
ipq807x: Enable CPU frequency scaling stats
Enable the CPU frequency scaling statistics in kernel config.

Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
Reviewed-by: Robert Marko <robimarko@gmail.com>
2023-01-31 16:33:21 +01:00
André Valentin
952c738c0f
ipq807x: add nvmem uboot-env support
Enabling kernel symbol CONFIG_NVMEM_U_BOOT_ENV allows to use u-boot
environement variable ethaddr with nvmen. That way it is possible to assign
the MAC address to the ethernet device driver.

Example of usage in dts:
....
	partition@600000 {
			compatible = "u-boot,env";
			label = "0:appsblenv";
			reg = <0x600000 0x10000>;

			macaddr_lan: ethaddr {
			};
	};
....
&dp5 {
	status = "okay";
	phy-handle = <&qca8081>;
	label = "wan";
	nvmem-cells = <&macaddr_lan>;
	nvmem-cell-names = "mac-address-ascii";
	mac-address-increment = <1>;
};

This is needed for Zyxel NBG7815.

Signed-off-by: André Valentin <avalentin@marcant.net>
2023-01-19 13:26:15 +01:00
Robert Marko
b5f32064ed ipq807x: add Qualcomm Atheros IPQ807x target
Qualcomm Atheros IPQ807x is a modern WiSoC featuring:
* Quad Core ARMv8 Cortex A-53
	* @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye
	* @ 1.4 GHz (IPQ8070A/1A) Codename Acorn
* Dual Band simultaneaous IEEE 802.11ax
	* 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A)
	* 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A)
	* 5G: 2x2/80MHz (IPQ8070A)
	* 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A)
	* 2G: 2x2/40MHz (IPQ8070A/1A)
* 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports)
* 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye
* 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn
* DDR3L/4 32/16 bit up to 2400MT/s
* SDIO 3.0/SD card 3.0/eMMC 5.1
* Dual USB 3.0
* One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane)
* Parallel NAND (ONFI)/LCD
* 6x QUP BLSP SPI/I2C/UART
* I2S, PCM, and TDMA
* HW PWM
* 1.8V configurable GPIO
* Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc)

Note that only v2 SOC models aka the ones ending with A suffix are
supported, v1 models do not comply to the final 802.11ax and have
lower clocks, lack the Gen3 PCIe etc.

SoC itself has two UBI32 cores for the NSS offloading system, however
currently no offloading is supported.

Signed-off-by: Robert Marko <robimarko@gmail.com>
2023-01-16 12:42:23 +01:00