Drop redundant label with new LED color/function format declared.
This was needed previously when the new format wasn't supported by
leds.sh functions script. Now that is supported this property
can be removed in favor of the new format.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The rtl93xx SoC supports both 1000Base-X and 10GBase-CR on its SerDes
interfaces. Enable dynamic switching between mac-signaled modes to
support 1000Base-X and 10GBase-CR on the SFP port.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch adds support for 1000Base-X and 10GBase-CR directly on the
SerDes lanes of rtl93xx SoCs.
This fixes SFP/SFP+ support on devices like the XSG1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
Commit daefc646e6 ("realtek: fix ZyXEL initramfs image generation")
fixed a shell expansion issue with zyxel-vers usage. Commit 045baca10b
("realtek: deduplicate GS1900 recipes") took care of this for the
rtl838x and rtl839x subtargets, but the single device officially
supported in rtl930x - the XGS1250-12 - was overlooked. This commit
updates the XGS1250-12 build recipe as well.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Backport merged upstream patch that adds support for firmware loader
from NVMEM or attached filesystem for Aquantia PHYs.
Refresh all kernel patches affected by this change.
Also update the path for aquantia .ko that got moved to dedicated
directory upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
[rmilecki: port to 5.15]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Refresh HSGMII patch due to recent PHY backport that cause
compilation warning for case not handled in phy_interface_num_ports.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The current dts file of dgs-1210-10p doesn't support link states
for the sfp ports (they are always up).
This patch tries to give better support for this and was run tested
on dgs-1210-10p.
It was heavily inspired from Paul Fertser, RaylynnKnight
and the author of dgs-1210-10mp-f.dts
https://forum.openwrt.org/t/dlink-dgs-1210-10p-with-glc-t-co-sfp/170928
Signed-off-by: Michel Thill <jmthill@gmail.com>
The register constants were duplicated in net/dsa/rtl83xx/debugfs.c and asm
mach-rtl838x/mach-rtl83xx.h. This commit removes this duplication.
Signed-off-by: Peter Körner <git@mazdermind.de>
According to https://svanheule.net/realtek/maple/register/led_sw_ctrl and also
drivers/net/dsa/rtl83xx/debugfs.c LED_SW_CTRL on the RTL838X should be 0xa00c
not 0x0128. Please note, that is is 0x0128 on the RTL8390/cypress SOC family.
Signed-off-by: Peter Körner <git@mazdermind.de>
the given code-format did not correctly express the condition and made the code
harder to read then necessary.
Signed-off-by: Peter Körner <git@mazdermind.de>
The GS110TUP v1 is a managed switch similar to the GS110TPP v1, but with
port 10 as SFP instead of RJ-45 and a total budget of 240 watts. Ports
1-4 support 60-watt 802.3bt PoE and ports 5-8 support 30-watt 802.3at.
The flash layout of the two switches are identical, and the U-Boot
configurations are the same except for having a different magic number,
so installation can be done via the same U-Boot method.
The following command will be needed to enable the port LEDs as per
https://forum.openwrt.org/t/72510/51 :
fw_setenv bootcmd "rtk network on; boota"
Additionally, port 9 (1000base-T from a separate QSGMII PHY) does not
function without this. Port 10 was not tested as no SFP module was
available.
Signed-off-by: Jacob Potter <jacob@j4cbo.com>
[rebase on merged flash layout]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.
Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before, PVID is reset for all ports and goes out of bounds. Also, PVID
is later changed by dsa configuration by `ip link` and `bridge vlan`
commands, this does not change the CPU port PVID and CPU PVID stays 0.
It does not allow sending packets from OpenWrt to any connected devices
unless default configuration is changed
This change iterates up to and including cpu_port and sets default PVID
to 1. For lan* ports PVID can be configured with `ip link` and `bridge
vlan` commands
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Fix incorrect register value being set for VLAN_PORT_FWD
Before, the 0b1111 would be set for the register which means outgoing
packets would receive an extra tag, corresponding to the PVID of the
port.
On untagged ports, this meant outgoing packets with a single tag.
On tagged ports, this meant outgoing QinQ packets, where the inner tag
was either the PVID of the untagged ingress port, or the already
assigned original (single) tag.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Without this, luci shows 10M full duplex when there is no link. So
explicitly set half duplex and unknown speed.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Use led_setX to determine number of LEDs per port. Introduce macros to
calculate register value and shift for particular LED in a particular
set.
Problem with previous implementation is that it uses is10G status to
determine leds per port. However with usxgmii, driver sets 10g, 5g and
2.5g so even though there are only 2 leds per port it selects 4 leds per
port
This implementation relies on configured led_set node.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Before driver code
- enabled egress filter for cpu and non-cpu ports
- enabled ingress filter for non-cpu ports
This patch explicitly enables ingress and egress filtering for non-cpu
ports and disables ingress and egress filtering for cpu port.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Currently OpenWRT does not know how to properly reset the network switch. This would result in
a switch that seemed to come up properly but was unable to handle any traffic. Presumably something
earlier in the boot chain is configuring a part of the switch that gets wiped out when its reset.
For now comment out the reset GPIO entry in the device tree until the driver better supports
bringing up the switch after a reset.
Signed-off-by: Michael 'ASAP' Weinrich <michael@a5ap.net>
The upper 16 bits of the 32 bit value encode the SoC model in BCD
notation (for example 0x83806800 on a Netgear GS108Tv3 with an
RTL8380M), so it makes more sense to output the value in hex notation
than in decimal notation.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
The MAC embedded in rtl93xx switch SoCs needs different mac mode bits set
to support 10BaseT and 100BaseT link modes. Set them accordingly.
This change has been tested on a ZyXEL XGS1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch cleans up and standardizes realtek-poe support for realtek
based switches that have supported PoE ports.
The power output of switches supported by realtek-poe package can be
configured in the 02_network ucidef_set_poe() function. This was missed
when some PoE capable switches supported by realtek-poe were added.
The realtek-poe package at one point replaced a lua-rs232 based script
and some devices were not updated to use the realtek-poe package.
Consistently add realtek-poe package to DEVICE_PACKAGES for switches
with supported PoE.
Signed-off-by: Raylynn Knight <rayknight@me.com>
This is an RTL8382-based switch with 24 copper ports + 4 SFP ports
Specifications:
---------------
* SoC: Realtek RTL8382M
* Flash: 32 MiB SPI flash
* RAM: 256 MiB
* Ethernet: 24x 10/100/1000 Mbps
* Buttons: 1x "Reset" button
* UART: 1x serial header, unpopulated
* SFP: 4 SFP ports
Works:
------
- (24) RJ-45 ethernet ports
- Switch functions
- Buttons
- Sys LED on front panel (no port LEDs)
Not yet enabled:
----------------
- Port LEDs (no driver for RTL8231 in this mode)
- SFP cages (no driver for PHY)
Install via web interface:
-------------------------
Not supported at this time.
Install via serial console/tftp:
--------------------------------
The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U6)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as soon as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWRT.
Blind install via tftp:
-----------------------
This method works when it's not feasible to install a serial header.
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
3. Watch network traffic (tcpdump or wireshark works)
4. Power on the device.
5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
6. When 192.168.0.30 makes tftp requests, release pin 16
7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Hardware information:
---------------------
- RTL8380 SoC
- 8 Gigabit RJ45 PoE ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
- PoE chip
- Fanless
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '65'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
There are two hardware models of the HPE 1920-8g-poe switch. The version
currently in the repository is the model with a PoE budget of 180W. In
preparation of the addition of the 65W model, the existing model is
renamed to clarify the hardware version it targets.
As suggested by Pawel, the 'SUPPORTED_DEVICES' includes the old target
name to enable an upgrade path of builds with the old name.
Suggested-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
Fix Spanning Tree Protocol (STP) by changing COPY2CPU which currently
makes switch to ignore Bridge Protocol Data Units (BPDUs).
Tested on Zyxel GS1900-8, 24 and 48.
Signed-off-by: Rudolf Vesely <i@rudolfvesely.com>
[ improve commit description and add new line in different sections ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The USXGMII implementation of Realtek switches can not only support
10GbE but also 2.5Gb and 5Gb on top of the usual data rates.
Mark those as supported to allow them to be negotiated.
This change has been tested on a ZyXEL XGS1250-12 with the following link
partners:
- NWA50AX Pro (2.5Gb)
- RTL8152 USB NIC (2.5Gb)
- AQC111 USB NIC (2.5Gb & 5Gb)
Gbit and 10GbE has also been tested to still work fine with a variety of
devices.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This condition was introduced in commit 51c8f76612 ("realtek: Improve
MAC config handling for all SoCs") to correctly report the speed of the
internal serdes ports as 10G, but instead makes all ports read 10G
because the or-operator should have been an and-operator.
Fixes: #9953
Fixes: 51c8f76612 ("realtek: Improve MAC config handling for all SoCs")
Signed-off-by: Peter Körner <git@mazdermind.de>
[ wrap comment to 72 column and improve commit ref ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Import commits from upstream Linux replacing some downstream patches.
Move accepted patches from pending-{5.15,6.1} to backport-{5.15,6.1}.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Hardware information:
---------------------
- RTL8380 SoC
- 8 Gigabit RJ45 PoE ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
- PoE chips: Nuvoton M0516LDE + BCM59121
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc002)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '180'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
To improve code readability in drivers/net/phy/rtl83xx-phy.c, replace
constants MMD_AN and MMD_VEND2 from drivers/net/phy/rtl83xx-phy.h with
MDIO_MMD_AN and MDIO_MMD_VEND2 from <linux/mdio.h>.
Also, replace
BIT(0) with MDIO_EEE_2_5GT,
BIT(1) with MDIO_EEE_100TX,
BIT(2) with MDIO_EEE_1000T,
BIT(9) with MDIO_AN_CTRL1_RESTART,
BIT(12) with MDIO_AN_CTRL1_ENABLE,
32 with MDIO_AN_10GBT_CTRL,
60 with MDIO_AN_EEE_ADV, and
62 with MDIO_AN_EEE_ADV2
from <linux/mdio.h>.
Suggested-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Replace BIT(x) and numerical values in drivers/net/phy/rtl83xx-phy.c
with constants from <linux/mii.h> to improve code readability.
To make reviewing easier, this commit only addresses ADVERTISE_* and
MII_PHYSID* constants.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Replace numerical values, BIT(x) and (1 << x) in
drivers/net/phy/rtl83xx-phy.c with constants from <linux/mii.h> to
improve code readability.
To make reviewing easier, this commit only addresses MII_BMCR and BMCR_*
constants.
Suggested-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Backport initial LEDs hw control support. Currently this is limited to
only rx/tx and link events for the netdev trigger but the API got
accepted and the additional modes are working on and will be backported
later.
Refresh every patch and add the additional config flag for QCA8K new
LEDs support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
One is never to write to dev->addr directly. In 6.1 it will be a const and
with the newly enabled WERROR, we get a failing grade.
Lets fix this ahead of time.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
We are missing a bunch of headers, which trigger errors on 6.1, probably
due to changed header-in-header dependencies. Best add them now.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Backport commits adding support for the MT7988 built-in switch to the
mt7530 driver.
This change results in the Kconfig symbol NET_DSA_MT7530 to be extended
by NET_DSA_MT7530_MDIO (everything formally covered by NET_DSA_MT7530)
and NET_DSA_MT7530_MMIO (a new driver for the MMIO-connected built-in
switch of the MT7988 SoC).
Select NET_DSA_MT7530_MDIO for all targets previously selecting
NET_DSA_MT7530, with the exception of mediatek/filogic which also
selects NET_DSA_MT7530_MMIO.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
All targets are bumped to 5.15. Remove the old 5.10 patches, configs
and files using:
find target/linux -iname '*-5.10' -exec rm -r {} \;
Further, remove the 5.10 include.
Signed-off-by: Nick Hainke <vincent@systemli.org>
Replace fallthrough comment with fallthrough macro for rtl838x ethernet
driver.
Fix compilarion warning:
drivers/net/ethernet/rtl838x_eth.c: In function 'rtl930x_mdio_reset':
drivers/net/ethernet/rtl838x_eth.c:1959:43: error: this statement may fall through [-Werror=implicit-fallthrough=]
1959 | private_poll_mask |= BIT(i);
drivers/net/ethernet/rtl838x_eth.c:1961:17: note: here
1961 | case PHY_INTERFACE_MODE_USXGMII:
| ^~~~
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix uninizialized variable in rtl83xx qos driver
Fix compilation error:
drivers/net/dsa/rtl83xx/qos.c: In function 'rtl838x_setup_prio2queue_matrix':
drivers/net/dsa/rtl83xx/qos.c:298:19: error: 'v' is used uninitialized [-Werror=uninitialized]
298 | v |= i << (min_queues[i] * 3);
| ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/qos.c:294:13: note: 'v' was declared here
294 | u32 v;
| ^
drivers/net/dsa/rtl83xx/qos.c: In function 'rtl83xx_setup_prio2queue_cpu_matrix':
drivers/net/dsa/rtl83xx/qos.c:320:19: error: 'v' is used uninitialized [-Werror=uninitialized]
320 | v |= max_queues[i] << (i * 3);
| ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/qos.c:316:13: note: 'v' was declared here
316 | u32 v;
| ^
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Comment unused part of realtek phy driver.
Fix compilation warning:
drivers/net/phy/rtl83xx-phy.c: In function 'rtl8380_configure_int_rtl8218b':
drivers/net/phy/rtl83xx-phy.c:747:21: error: unused variable 'ipd_flag' [-Werror=unused-variable]
747 | int ipd_flag = 1;
| ^~~~~~~~
drivers/net/phy/rtl83xx-phy.c: At top level:
drivers/net/phy/rtl83xx-phy.c:3333:13: error: 'rtl931x_sds_disable' defined but not used [-Werror=unused-function]
3333 | static void rtl931x_sds_disable(u32 sds)
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment unused part of realtek dsa driver.
Fix compilation warning:
drivers/net/dsa/rtl83xx/common.c: In function 'rtl83xx_fib_event':
drivers/net/dsa/rtl83xx/common.c:1430:58: error: unused variable 'fen6_info' [-Werror=unused-variable]
1430 | struct fib6_entry_notifier_info *fen6_info = ptr;
| ^~~~~~~~~
drivers/net/dsa/rtl83xx/common.c: At top level:
drivers/net/dsa/rtl83xx/common.c:531:12: error: 'rtl83xx_octet_cntr_alloc' defined but not used [-Werror=unused-function]
531 | static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Drop unused priv in realtek dsa driver.
Fix compilation warning:
drivers/net/dsa/rtl83xx/dsa.c: In function 'rtl83xx_port_lag_change':
drivers/net/dsa/rtl83xx/dsa.c:2016:37: error: unused variable 'priv' [-Werror=unused-variable]
2016 | struct rtl838x_switch_priv *priv = ds->priv;
| ^~~~
cc1: all warnings being treated as errors
Comment rtl838x_pie_rule_dump in realtek dsa driver for rtl83xx
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl838x.c:1294:13: error: 'rtl838x_pie_rule_dump' defined but not used [-Werror=unused-function]
1294 | static void rtl838x_pie_rule_dump(struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment multiple function in realtek dsa driver for rtl930x
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl930x.c:1463:12: error: 'rtl930x_l3_intf_add' defined but not used [-Werror=unused-function]
1463 | static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
| ^~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:1414:12: error: 'rtl930x_l3_mtu_del' defined but not used [-Werror=unused-function]
1414 | static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
| ^~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:995:12: error: 'rtl930x_l3_hash6' defined but not used [-Werror=unused-function]
995 | static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
| ^~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
drivers/net/dsa/rtl83xx/rtl930x.c:1690:13: error: 'rtl930x_read_pie_fixed_fields' defined but not used [-Werror=unused-function]
1690 | static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:1432:12: error: 'rtl930x_l3_mtu_add' defined but not used [-Werror=unused-function]
1432 | static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment rtl931x_read_pie_fixed_fields in realtek dsa driver for rtl931x
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl931x.c:1116:13: error: 'rtl931x_read_pie_fixed_fields' defined but not used [-Werror=unused-function]
1116 | static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment rtl93xx_header_vlan_set in realtek ethernet driver for rtl838x
Fix compilation warning:
drivers/net/ethernet/rtl838x_eth.c: At top level:
drivers/net/ethernet/rtl838x_eth.c:164:13: error: 'rtl93xx_header_vlan_set' defined but not used [-Werror=unused-function]
164 | static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
| ^~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Rework exposing i2c_mii_valid_phy_id and i2c_mii_phy_addr in global
include.
Fix compilation warning:
In file included from drivers/net/phy/sfp.c:11:
./include/linux/mdio/mdio-i2c.h:27:21: error: 'i2c_mii_phy_addr' defined but not used [-Werror=unused-function]
27 | static unsigned int i2c_mii_phy_addr(int phy_id)
| ^~~~~~~~~~~~~~~~
./include/linux/mdio/mdio-i2c.h:22:13: error: 'i2c_mii_valid_phy_id' defined but not used [-Werror=unused-function]
22 | static bool i2c_mii_valid_phy_id(int phy_id)
| ^~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
PHY_INTERFACE_MODE_HSGMII was not handled in phylink_get_linkmodes and
phylink_parse_mode.
Fix compilation warning by adding it in the enum:
drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes':
drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_HSGMII' not handled in switch [-Werror=switch]
360 | switch (interface) {
| ^~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
All callers of the rtl83xx_mc_group_* functions already do the same
check, so these aren't needed.
For rtl83xx_mc_group_alloc, this branch also incorrectly returned 0
instead of a negative value. If the branch wasn't effectively dead code
anyway, this could potentially have caused bugs, as 0 is a valid
multicast group entry index.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The current implementation only works when store and load are called for
the same port without any other calls in between. This is because the
store function only saves a single port number instead of a portmask for
each group. It also doesn't take into account that the allocation of
multicast group entries might change between store/load calls.
As a result, the multicast port mask table gets corrupted. This also
includes the reserved entry for unknown multicast, which gets corrupted
even when no other mdb entries have been added.
Remove the code for storing/loading multicast groups entirely, as the
original commit message doesn't offer a convincing reason why this would
be necessary in the first place.
Fixes: 724e4af530 ("realtek: Store and Restore MC memberships for port enable/disable")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
There shouldn't be any reason to forward all multicast to the CPU. The
original commit message also doesn't provide a reason for this seemingly
unrelated change.
The current implementation of the delete method is also broken, as it
entirely removes any entry when the portmask contains only the CPU port,
even if it was explicitly created.
Fixes: 724e4af530 ("realtek: Store and Restore MC memberships for port enable/disable")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
There doesn't appear to be a reason to do this, as only the last entry
is actually reserved for unknown multicast.
This also fixes two issues:
- As the increment happened after the bounds check, the value of the
actually reserved last entry could be overwritten.
- On deletion of entries, a corresponding decrement was missing,
causing the wrong entry to be marked as free.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Actually use the index returned by rtl83xx_find_l2_cam_entry.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The port_vlan_add method may be called while a port is already a member
of that VLAN, so it needs to be able to handle changed flags. Fix it to
properly handle when the PVID or UNTAGGED flag was previously set, but
now no longer is.
To reduce duplication, move PVID configuration to a separate function.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The registers L2_PORT_STATIC_MV_ACT seem to specify the action to take
when the source address of a packet exists as a static fdb entry on
another port. By default the configured action is to drop such packets.
For standalone ports, this behaviour is undesired, as all traffic should
be forwarded to the CPU. So change the action to forward on standalone
ports.
A situation where this issue can occur is when a non-offloaded bond
interface is part of a bridge. In that case, the CPU port will have fdb
entries for devices connected to the bond interface, which are managed
by the assisted learning feature.
For now, this is only implemented for RTL838x/RTL839x, as the available
set of registers differs for the other devices.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
All ports are disabled by default, so configure the port isolation masks
and the pm field accordingly in the setup function. When port_enable is
called for a port, the isolation masks will be set up so that traffic
can flow between the port and the CPU.
While at it, change the code to also use the traffic_set method in
rtl83xx_setup, instead of writing to the RTL838x_PORT_ISO_CTRL(i)
registers directly.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Correctly update the isolation mask of the port being configured. The
port_bitmap variable should contain all other bridge members and needs
to be actually removed from the isolation mask instead of added to it.
Also actually remove the port being configured from the pm field of the
other ports, so that any other ports that are currently disabled will be
configured correctly when they are enabled.
Fixes: df8e6be59a ("rtl838x: add new architecture")
[fixed updating pm field of other ports]
Fixes: 2b88563ee5 ("realtek: update the tree to the latest refactored version")
[reintroduced incorrect pm field update]
Fixes: 27029277f9 ("realtek: add switch driver support for the RTL93XX based switches")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The switch driver actually expects every port to have a PHY handle, and
several branches in the code determine if a port is valid by checking
for a non-zero phy field.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The legacy (BSD) PTY support could open security problems in a system,
We do not need them in OpenWrt, deactivate this option in all targets.
Debian also deactivates this option.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Fix mis-typed DEVICE-MODEL in mk file for EnGenius EWS2910P.
Signed-off-by: Raylynn Knight <rayknight@me.com>
[ fix wrong SoB format and improve commit title/description ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Refresh patches which were no longer applying cleanly after a recently
added SFP quirk.
Fixes: 658b45ce48 ("generic: add quirk for HG MXPD-483II 2500M fiber SFP")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
APRESIA ApresiaLightGS120GT-SS (APLGS120GTSS) is a 16 + 4 ports gigabit
switch, based on RTL8382M.
Specifications:
- SoC : Realtek RTL8382M
- RAM : DDR3 256 MiB (Nanya NT5CC256M8JQ-EK)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x16 + 4
- port 1-8 : RTL8218B
- port 9-16 : RTL8382M, TP (SoC, RTL8218B)
- port 17-20 : RTL8214FC, TP/SFP (Combo)
- LEDs/Keys : 3x/1x
- UART : through-hole on PCB
- J6: 3.3V, TX, RX, GND from tri-angle marking side
- 115200n8
- Power : 100-120/200-240 VAC, 50/60 Hz
Max. 16 W, Avg 14 W (100 VAC)
- Plug : IEC 60320-C13
Flash instruction using factory image:
1. Boot ApresiaLightGS120GT-SS normally
2. Login to WebUI and open firmware page ("ファームウェア")
3. If the device is booted from image1, set active image for next
booting ("起動イメージ選択") to image2("イメージ2"), press apply
("適用") button and reboot the device to make booting from image2
4. On the WebUI, set active image to image1
5. Select the OpenWrt factory image and press update button ("更新")
6. Open reboot page ("再起動") and press reboot button ("再起動実行")
Notes:
- "ApresiaLightGS120GT-SS" is a model name and "APLGS120GTSS" is a model
number
- this device has 3x GPIO-controlled LEDs on PCB, but 1x LED
("green:unused") has no hole on the case
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The cameo-related recipes can also be used for APRESIA ApresiaLightGS
series devices. So create common definition for the devices manufactured
by Cameo.
And also, the model name of ApresiaLightGS120GT-SS is too long for cameo
header (max: 20 bytes), so use additional variable "CAMEO_BOARD_MODEL"
in Build/cameo-headers instead of DEVICE_MODEL to use the custom name.
(default of CAMEO_BOARD_MODEL: DEVICE_MODEL)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch renames some Cameo specific definitions for image generation.
The same format is also used on APRESIA ApresiaLightGS series devices, not
D-Link specific.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The net_event_work struct is allocated, but only freed in a single case.
Move the allocation to the branch where it is actually needed, and free
it after the work has been done.
Fixes: 03e1d93e07 ("realtek: add driver support for routing offload")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Use generic earlycon on Linux Kernel instead of initialization in platform
setup.
And also, drop bootargs with console= parameter from I-O DATA BSH-G24MB. It
uses 115200bps as baud-rate, the same as default in rtl838x.dtsi.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
On the realtek target, the subtarget makefiles include a KERNEL_PATCHVER
setting, shadowing KERNEL_PATCHVER from target/linux/realtek/Makefile.
This makes the realtek target an exception in this regard, and makes
switching kernel version a bit bothersome. Remove the overrides so all
subtargets use the same kernel version.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Adjust the wrong phy-handle definitions for the sfp ports so that they
match the correct switch ports.
Fixes: 89eb8b50d1 ("realtek: dgs-1210-10mp: add full sfp description")
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
Make the patches apply cleanly again.
Fixes: 4db8598e42 ("realtek: Do not set KERNEL_ENTRY just to avoid NO_EXCEPT_FILL")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use the new timer driver for the RTL930x devices.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[remove old clock provider, select MIPS_EXTERNAL_TIMER and refresh
kernel config]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before calling sched_clock_register(), the timer used to drive the
scheduling clock should already be enabled. Otherwise the kernel log
will show strange time jumps during, and the watchdog might not be
pinged in a timely fashion, resulting in reboots.
[ 0.160281] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 78.104319] clocksource: Switched to clocksource realtek_otto_timer
Fixes: 3cc8011171 ("realtek: resurrect timer driver")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Because this comment is followed by another comment, nothing luckily
breaks, so only a cosmetic change.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
RTL931x kernel builds were patched to bypass the LINKER_LOAD_ADDRESS
parameter, and hardcode it to 0x80220000. This doesn't make much sense,
since value of LINKER_LOAD_ADDRESS, load-ld, only appears to be a copy
of load-y, adjusted to the linker's taste.
Dropping the hacks for bypassing LINKER_LOAD_ADDRESS results in a kernel
that actually starts booting on an RTL9313 (Netgear MS510TXM), but
currently still hangs when the kernel switches timers.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The TP-LINK TL-ST1008F has active-high LEDs, so we need a device tree
property to express this.
Signed-off-by: Lorenz Brun <lorenz@brun.one>
[Tidy up code, restrict changes to 5.15]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
On RTL931x builds, CONFIG_RTL931X was used as a stand-in for
CONFIG_NO_EXCEPT_FILL. Now that the latter is always selected for
devices in the realtek target, this hack can be removed. Resulting
device images are binary identical.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
It seems like we are offsetting the KERNEL_ENTRY to +0x400, which is
also accomplished by the NO_EXCEPT_FILL configuration option.
Since this is the default for MIPS_GENERIC_KERNEL, lets push a little
bit closer to that one by doing the same thing.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
After commit e0d2c59ee995 ("genirq: Always limit the affinity to online
CPUs", 5.10) on Linux, the cpumask passed to irq_set_affinity of irqchip
driver is limited to online CPUs. When irq_do_set_affinity called from
otto timer driver with only one secondary CPU, that CPU is not marked as
online yet, filtered out by cpu_online_mask and fall to error path.
Then, fail to set affinity for that CPU and it leads to instability of
timer on secondary CPU(s).
At least, RTL839x system will be affected.
log:
[ 37.560020] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 37.638025] rcu: 1-...!: (0 ticks this GP) idle=6ac/0/0x0 softirq=0/0 fqs=1 (false positive?)
[ 37.752683] (detected by 0, t=6002 jiffies, g=-1179, q=26293)
[ 37.829510] Sending NMI from CPU 0 to CPUs 1:
[ 37.886857] NMI backtrace for cpu 1 skipped: idling at r4k_wait_irqoff+0x1c/0x24
[ 37.984801] rcu: rcu_sched kthread timer wakeup didn't happen for 5999 jiffies! g-1179 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402
[ 38.132743] rcu: Possible timer handling issue on cpu=1 timer-softirq=0
[ 38.221033] rcu: rcu_sched kthread starved for 6000 jiffies! g-1179 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=1
[ 38.356336] rcu: Unless rcu_sched kthread gets sufficient CPU time, OOM is now expected behavior.
[ 38.474440] rcu: RCU grace-period kthread stack dump:
...
Replace to irq_force_affinity from irq_set_affinity and ignore
cpu_online_mask to fix the issue.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Tested-by: Olliver Schinagl <oliver@schinagl.nl>
While Linus is fine with longer code lines, comments should still be
within the 80 char limit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This is an RTL8393-based switch with 48 RJ-45 and 2 SFP ports.
Hardware
--------
SoC: Realtek RTL8393M
RAM: 128MB DDR3 (Nanya NT5CC64M16GP-DI)
FLASH: 8MB NOR (Macronix MX25L6433F)
ETH: 48x 10/100/1000 Mbps RJ-45 Ethernet
SFP: 2x SFP
BTN:
- 1x Reset button
LEDS:
- 50x Green-Amber leds: lan/sfp status
- 1x Green led: power (Always on)
UART:
- 115200-8-N-1 (CN3, pin-out on PCB)
Everything works correctly except for the 2 SFP ports that are not
working unless you enable it every boot in U-Boot with the command:
rtk network on
Installation
------------
You can install Openwrt using one of the following methods.
Warning: flashing OpenWrt will delete your current configuration.
Warning 2: if the -factory.bix file is not available anymore, you must
follow Method 2.
Method 1:
Check the firmware version currently running on your switch. If you are
running FW V1.0.1.10 or greater, you have to download the firmware
V1.0.1.8 from Netgear website and then flash this version. When the
switch restarts, it should be on version V1.0.1.8. Now you can get the
OpenWrt -factory.bix file and then flash it using the OEM web interface.
Method 2 (requires the UART connection):
Boot the -initramfs-kernel.bin image from U-Boot with these commands:
rtk network on;
tftpboot 0x8f000000 openwrt-realtek-rtl839x-netgear_gs750e-initramfs-kernel.bin;
bootm;
And then flash the -sysupgrade.bin file from OpenWrt.
Revert to stock
---------------
Get the stock firmware from the Netgear website and flash it using the
OpenWrt web interface. Remember to not keep the current configuration
and check the "Force upgrade" checkbox
Once reverted to stock the firmware could complain in the UART console
about mtdblock3 and/or mtdblock4 not being mounted correctly but it
seems to work anyway without any problems. Sample error:
mount: Mounting /dev/mtdblock4 on /mntlog failed: Input/output error
If you want to get rid of these error messages you can boot the
-initramfs-kernel.bin image from U-Boot with these commands:
rtk network on;
tftpboot 0x8f000000 openwrt-realtek-rtl839x-netgear_gs750e-initramfs-kernel.bin;
bootm;
And then erase the corresponding partitions using the command:
For mtdblock3:
mtd erase jffs2_cfg
For mtdblock4:
mtd erase jffs2_log
Now you can reboot the switch and the errors should be gone
Note
----
To get the SFP ports fully working, all the right GPIOs must be found.
In the GPL sources I found these:
- GPIO_14: SFP_TX_DIS1;
- GPIO_19: SFP_TX_DIS0;
Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
Make the patches apply cleanly again.
Fixes: 8dfe69cdfc ("kernel: update nvmem subsystem to the latest upstream")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Added the full SFP description for both SFP ports (lan9, 10) on D-Link
DGS-1210-10MP, which enables hot-plug detection of SFP modules.
Added the patch to both kernel 5.10 and 5.15 dts files.
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
Make the patches apply cleanly again.
Fixes: 8dfe69cdfc ("kernel: update nvmem subsystem to the latest upstream")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is no longer needed now that the kernel is built with a load
address that matches the one hard-coded in the bootloader.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
In target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c,
make rtl838x_pie_rule_write() return non-zero value case of error.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Make sure functions calling rtl838x_smi_wait_op() return its return
value in target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c.
This brings the code style in line with the rtl839x implementation.
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
A behavioural change was introduced with commit 758c88b969 ("realtek:
Whitespace and codestyle cleanup") causing rtl838x_read_phy() and
rtl838x_write_phy() to unconditionally return -ETIMEDOUT. As a result,
probing the device during boot fails:
Error setting up netdev, freeing it again.
rtl838x-eth: probe of 1b00a300.ethernet failed with error -5
Fix the bootloop caused by this regression with kernel 5.15 on rtl838x
devices, by properly returning 0 on success.
Tested on a Netgear GS108T v3, a Netgear GS310TP v1, a Zyxel GS1900-8HP
v1 and an HPE 1920-8G.
Fixes: 758c88b969 ("realtek: Whitespace and codestyle cleanup")
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Upstream generic MIPS uses 0x80100000 and 0x80100400 for the LOADADDR
and ENTRY addresses. As we do not want to diverge from upstream and
patch upstream when not needed, adjust our addresses as well to be
future proof.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
ZyXEL GS1900 devices with SoCs from both the RTL838x and RTL839x
families share the same image structure and size of the firmware
partition. Additionally, the GS1900-48 recipe provided a parameter for
the zyxel-vers command, but this parameter is not used. Deduplicate the
recipes by moving it to target/linux/realtek/image/common.mk.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The listed partition size doesn't match the original partition size, and
actually overlaps with the following partition. The partition node name
for the "firmware" partition also has an extra 'b' compared to the
partition offset.
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900-48 firmware image is identified by the 'AAHN' ID, while the
GS1900-48HP is identified by 'AAHO' [1]. The latter was used, resulting
in the following error message when upgrading via the stock web UI:
Device only can support firmware from V1.00(AAHN.0) and later version
Fix image generation by using the correct ID.
[1] https://download.zyxel.com/GS1900-48/firmware/GS1900-48_2.70(AAHN.3)C0_2.pdf
Link: https://forum.openwrt.org/t/146533
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Suggested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
While cleaning up the makefiles for the realtek target, the order of the
default image generating commands was accidentally changed. This caused
the image signature to end up somewhere in the middle, misaligning the
rootfs. As a result, sysupgrade couldn't verify upgrade images anymore,
and devices end up in a boot loop due to the unaligned (and not found)
rootfs.
Fixes: 94d8b4852b ("realtek: Cleanup Makefiles")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The reset register on RTL93xx not merely have bits to execute
a reset of a hardware component, but also configuration bits for
reset procedures. Keep them during executing a reset.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[backport to 5.10 kernel]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Linus prefers to have loop initializers nice and tightly scoped. In
OpenWRT this has been possible since 41a1a652fb ("kernel: backport
gnu11 upgrade").
This patch cleans up variable scope while trying to do the above for
'simple for loops'.
This cleans up and simplifies some functions and code, and pulls in
variables to a smaller scope.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Our current Makefiles a little bit messy and can be improved somewhat,
both in whitespace and in style.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
The only exception to C++ style comments are SPDX license identifier
markers at the start of C files (even headers have C style markers).
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Fix some ugly whitepsaces and codestyle issues around the realtek sources.
While this is by no means perfect, it catches what it caught.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
A full loop accessing all FDB entries can take several milliseconds
(on RTL839x about 20 ms), so give other kernel tasks a chance to run.
This is especially important for rtl83xx_port_fdb_dump which is itself
called in a loop for all ports by the kernel.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
These two functions are identical apart from writing different values to
the read/write bit. Create a new function rtl_table_exec to reduce code
duplication.
Also replace the unbounded busy-waiting loop. The new implementation may
sleep, but as the hardware typically responds before the first poll, any
callers doing many table accesses still need to make sure not to block
other kernel tasks themselves.
So far, polling timeout errors are only handled by logging an error, but
a return value is added to allow proper handling in the future.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
This function currently prints three messages for every switch port at
KERN_INFO level. This takes a considerable amount of time during bootup
and can even trigger an external watchdog.
Replace these log messages by a single one at KERN_DEBUG level.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
As learning for the CPU port is now disabled globally, the bit in the
TX header doesn't have any effect anymore. Remove it to make the header
consistent with the global configuration.
Originally, this change was intended to be applied before commit
eb456aedfe ("realtek: use assisted learning on CPU port"), which is
why the commit message incorrectly mentions that the TX header already
disables learning.
The reason for disabling learning on the CPU port in the first place is
that it doesn't work correctly when packets are trapped to the CPU and
then forwarded by the CPU to other ports. In that case, the switch would
incorrectly learn the CPU port as source. An example that triggered this
issue are Multicast Listener Reports and IGMP membership reports.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
- rtl83xx_vlan_filtering()
"struct switchdev_trans *trans" parameter was removed[1] and
"struct netlink_ext_ack *extack" was added[2].
[1]: https://www.spinics.net/lists/netdev/msg712250.html
[2]: https://www.spinics.net/lists/netdev/msg722496.html
- rtl83xx_vlan_add/del()
vlan->vid_begin and vlan->vid_end were removed and vlan->vid was
added[3].
[3]: https://www.spinics.net/lists/netdev/msg712248.html
- rtl83xx_vlan_prepare()
"port_vlan_prepare" member was removed from "dsa_switch_ops" struct
in dsa.h[4] and vlan_prepare function should be called from vlan_add
function. Also, change return type of vlan_add function to int.
[4]: https://www.spinics.net/lists/netdev/msg712252.html
- rtl83xx_port_mdb_add()
"port_mdb_prepare" member in "dsa_switch_ops" struct was removed and
preparation need to be done in the function of "port_mdb_add" member
instead. And also, int type need to be returned on "port_mdb_add"
member[5].
[5]: https://www.spinics.net/lists/netdev/msg712251.html
- rtl83xx_port_pre_bridge_flags(), rtl83xx_port_bridge_flags()
The current "port_pre_bridge_flags" member and "port_bridge_flags"
member in "dsa_switch_ops" in dsa.h has flags of
"struct switchdev_brport_flags" type instead[6], so adjust to it.
And, the changed features are passed by flags.mask[7] in
rtl83xx_port_bridge_flags(), so check it before calling function
to enable/disable fieature.
[6]: https://lore.kernel.org/lkml/20210212151600.3357121-7-olteanv@gmail.com/
[7]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e18f4c18ab5b0dd47caaf8377c2e36d66f632a8c
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[shorten final return statement of rtl83xx_port_mdb_add()]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
- 007-5.16-gpio-realtek...: upstreamed on 5.16 and backported to 5.15.3
- 708-brflood-spi.patch : upstreamed
- 709-lag-offloading.patch: upstreamed
- 713-v5.12-net-dsa-... : upstreamed and some implementations are
replaced
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The following drivers were upstreamed and available on 5.15, so drop
from OpenWrt tree.
- realtek-otto-gpio (5.13)
- realtek-rtl-spi (5.12)
- realtek-rtl-intc (5.12)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
add three missing LEDs
- PoE-Max
- Link/Act
- PoE
add two missing buttons
- mode
- reset
The last was dropped in
commit 61a3d0075b ("realtek: update GPIO bindings in the dts files in dts-5.10")
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
General hardware info:
----------------------
D-Link DGS-1210-28MP rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC @ 500MHz,
DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 370W.
Power over Ethernet:
--------------------
The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU.
In order to enable PoE, the realtek-poe package is required. It is
installed by default, but currently it requires the manual editing of
/etc/config/poe. Keep in mind that the port number assignment does not
match on this switch, alway 8 ports are in reversed order: 8-1, 16-9 and
24-17.
LEDs and Buttons:
-----------------
On stock firmware, the mode button is supposed to switch the LED indicators
of all port LEDs between Link Activity and PoE status. The currently
selected mode is visualized using the respective LEDs. PoE Max indicates
that the maximum PoE budget has been reached.
Since there is currently no support for this behavior, these LEDs and
the mode button can be used independently.
Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.
Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
OEM installation from Web Interface:
------------------------------------
1. Make sure you are booting using OEM in image 2 slot. If not, switch to
image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image in vendor firmware via Tools > Backup / Upgrade
Firmware > image1
3. Toogle startup image via System > Firmware Information > Boot from
image1
4. Tools > reboot
Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:
Boot initramfs image from U-Boot:
---------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000
openwrt-rtl838x-generic-d-link_dgs-1210-28mp-f-initramfs-kernel.bin`
command
5. Boot the image with `bootm` command
Signed-off-by: Andreas Böhler <dev@aboehler.at>
should be add/delete or abbreviated add/del
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
The code in dsa.c:rtl83xx_port_enable() was trying to set
vlan_port_tag_sts_ctrl while dealing with differences between SoCs.
However, not only that register has a different address, the register
structure and even the 2-bit value semantic changes for each SoC.
The vlan_port_tag_sts_ctrl field was dropped and converted into a
vlan_port_keep_incoming_tag_set() function that abstracts the different
between SoCs. The macro referencing that register migrated to the SoC
specific c file as it will be privately used by each file.
All magic numbers were converted into macros using BITMASK and
FIELD_PREP.
The vlan_port_tag_sts_ctrl debugfs was dropped for now as it is already
broken for rtl93xx. The best place for SoC specific code might be in each
respective c file and not in if/else clauses.
The final result is:
rtl838x: set ITAG_STS=TAGGED, same as before
rtl839x: set ITAG_STS=TAGGED instead of IGR_P_ITAG_KEEP=0x1, fixing
forwarding of tagged packets
rtl930x: set EGR_ITAG_STS=TAGGED instead of IGR_P_ITAG=0x1, possibly
fixing forwarding of tagged packets
rtl931x: set EGR_ITAG_STS=TAGGED instead of OTPID_KEEP=0x1, possibly
fixing forwarding of tagged packets
Without (EGR_)ITAG_STS=TAGGED, at least for rtl839x, forwarded packets
will drop the vlan tag while packets from the CPU will still have the
correct tag.
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
The rtl930x speed status registers require 4 bits to indicate the speed
status. As such, we want to divide by 8. To make things consistent with
the rest of this code, use a bitshift however.
This bug probably won't affect many users yet, as there aren't many
rtl930x switches in the wild yet with more then 10 ports, and thus a
low-impact bugfix.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[also fix port field extraction]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
After replacing the R4K event timer and clock source with the new
Realtek Otto timer, performance for RTL839x devices was severely
impacted, as reported by Hiroshi.
Research by Markus showed that after commit 4657a5301e ("realtek:
avoid busy waiting for RTL839x PHY read/write"), the ethernet driver
could only update a phy once per timer interval, which also heavily
impacted boot time. On e.g. a Zyxel GS1900-48, this added around a
minute to the time to fully initialise the switch.
By marking the otto clocksource as continuous, the kernel enables it to
be used for high resolution timers. This allows readx_poll_timeout() to
sleep for less than one system timer interval, reducing system dead
time.
Link: https://github.com/openwrt/openwrt/issues/11117
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Cc: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
