Upstream handling of MIPS CPU IRQs is rather hackish and the interrupts
are being enabled unconditionally in various places because of legacy
code.
Performance counter events are routed both through the GIC and through
legacy CPU IRQ7 events, causing spurious interrupts.
Fix this by disabling IRQ7 when trying to access the performance counter
IRQ.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
