Add missing reset bits of USB phys on QCA955x SoCs to qca955x.dtsi to
handle them.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16297
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add aliases with "serialN = &uartN;" of uart0/1 on QCA955x SoCs to
qca955x.dtsi, to enable uart1 on Linux Kernel.
without this:
[ 0.342915] ar933x-uart 18500000.uart: unable to get alias id, err=-19
Additionally, remove "serial0 = &uart;" alias from QCA955x device
dts/dtsi files.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Add HighSpeed UART support to QCA955x series SoCs as a secondary UART
(uart1). This UART is compatible with qca,ar9330-uart.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Rename the DT label of the primary UART on Qualcomm Atheros QCA955x
series SoCs to "uart0" from "uart" for the preparation to add HighSpeed
UART (uart1) support.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
pcie-controller was renamed to pcie since at least kernel 4.14. Match it
here to get rid of dtc warnings.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
For all SoC in the ath79 target, the PLL controller provides 3 main
clocks "cpu", "ddr" and "ahb" through the input clock "ref".
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
ar9344_openmesh_mr600-v1.dts:40.10-44.5: Warning (gpios_property):
/leds-ath9k/wifi2g: Missing property '#gpio-cells' in node
/ahb/pcie-controller@180c0000/wifi@0,0 or bad phandle
=> added gpio-controller + #gpio-cells
qca955x_zyxel_nbg6x16.dtsi:121.3-13: Warning (reg_format):
/ahb/usb@1b000000/port@1:reg: property has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
../dts/qca955x_zyxel_nbg6x16.dtsi:131.3-13: Warning (reg_format):
/ahb/usb@1b400000/port@1:reg: property has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
qca955x_zyxel_nbg6x16.dtsi:120.20-123.4: Warning (avoid_default_addr_size):
/ahb/usb@1b000000/port@1: Relying on default #address-cells value
=> ath79's usb-nodes are missing the address- and size-cells properties.
These are needed for usb led trigger support.
ar7242_ubnt_sw.dtsi:54.4-14: Warning (reg_format): /gpio_spi/gpio_spi@0:reg:
property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)
=> the #address-cells and #size-cells had to be nudged.
qca9531_dlink_dch-g020-a1.dts:19.6-39.4: Warning (i2c_bus_bridge):
/i2c: incorrect #size-cells for I2C bus
=> #size-cells = <0>;
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.
Where the majority of devices is using it, also move the serial0
alias to the DTSI.
*) Since GL-USB150 even defines serial0 alias, the missing uart
is probably just a mistake. Anyway, disable it for now so this
patch stays cosmetic.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Specify the device_type property for PCI as well as PCIe controllers.
Otherwise, the PCI range parser will not be selected when using kernel
5.10.
Signed-off-by: David Bauer <mail@david-bauer.net>
ath79.dtsi uses ATH79_CLK_MDIO, so the include
<dt-bindings/clock/ath79-clk.h>
needs to be moved there.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
In ath79, for several SoCs the console bootargs are defined to the
very same value in every device's DTS. Consolidate these definitions
in the SoC dtsi files and drop further redundant definitions elsewhere.
The only device without any bootargs set has been OpenMesh OM5P-AC V2.
This will now inherit the setting from qca955x.dtsi
Note that while this tidies up master a lot, it might develop into a
frequent pitfall for backports.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
There are at least 3 different chips in the Scorpion series of SoCs.
Rename the common DTSI to better reflect it's purpose for the whole
series.
Also rename the compatible bindings from qca,ar9557 and qca,qca9557
to qca,qca9550.
Signed-off-by: David Bauer <mail@david-bauer.net>
