The range of pinmux reg property "<0x1804002c 0x40>" for QCA956x SoC
does not includes GPIO_FUNCTION register.
If the device uses "&jtag_disable_pins", this causes the following
errors:
[ 1.982937] pinctrl-single 1804002c.pinmux: mux offset out of range: 0x40 (0x40)
[ 1.990622] pinctrl-single 1804002c.pinmux: could not add functions for pinmux_jtag_disable_pins 64x
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The qca9557/qca956x reset-controller aren't a simple bus. A simple bus
would require node unit addresses.
Add the node unit addresses for the qca9557 usb phys. Add the regs for
the USB_PWRCTL and USB_CONFIG registers even not yet used.
Fix the wrong ar7100 pcie controller node unit address as well.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Fix all issues found by the devicetree compiler like wrong address/size
cells as well as wrong/missing/superfluous unit addresses.
Signed-off-by: Mathias Kresin <dev@kresin.me>
enable mdio1 by default because mdio1 node is a subnode of eth1
and eth1 node is a "simple-mfd", which makes mdio1 disabled when
eth1 isn't enabled.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This patch adds dts for qca956x and also support for Phicomm K2T
The qca965x.dtsi adds nearly all the necessary components.
Both ath9k AHB and PCIe worked well.
The Phicomm K2T uses MTD partition 'config' to store the mac addresses in
JSON format. To extract these fields correctly, a script is introduced:
/lib/functions/k2t.sh
This script provides a helper function to extract mac addresses, and is used
in three places.
Hardware spec of Phicomm K2T:
CPU: QCA9563
DRAM: 64MB DDR2
Flash: 16MB SPI-NOR
Switch: QCA8337
WiFi 5.8GHz: QCA9886
Flash instruction:
Apply sysupgrade.bin via serial console:
tftp 0x80000000 sysupgrade.bin && erase 0x9f090000 +$filesize && cp.b $fileaddr 0x9f090000 $filesize
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
