Rename the SoC-specific rtl838x_reg structure in the Ethernet
driver to avoid confusion with the structure of the same name
in the DSA driver. New name is: rtl838x_eth_reg
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Setting bits 20 and 23 in a u16 is obviously wrong.
According to https://www.svanheule.net/realtek/cypress/cputag
cpu_tag[2] starts at bit 48 in the cpu-tag structure, so
bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in
cpu_tag[2].
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger
contiguous memory allocation for the DMA of the Ethernet
driver. Increase the number of entries in the RX ring
to 300 making use of the larger DMA region now possible for
receiveing packets.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The GS1900-48 is a 48 + 2 port Gigabit L2 switch with 48 gigabit ports.
Hardware:
RTL8393M SoC
Macronix MX25l12805D (16MB flash)
128MB RAM
6 * RTL8218B external PHY
2 * RTL8231 GPIO extenders to control the port LEDs, system LED and
Reset button
2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.
Power is supplied via a 230 volt mains connector.
The board has a hard reset switch SW1, which is is not reachable from the outside.
J4 provides a 12V RS232 serial connector which is connected through U8 to
the 3.3V UART of the RTL8393. Conversion is done by U8, a SIPEX 3232EC.
To connect to the UART, wires can be soldered to R603 (TX) and R602 (RX).
Installation:
Install the squashfs image via Realtek's original Web-Interface.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Update the IRQ configuration to work with the new rtl-intc controller.
Also change all KSEG1 addresses in reg = <> of the devics to physical
addresses.
Use the new gpio-otto controller instead of the legacy driver.
Also remove the memory node as this is better put into a device .dts.
Also remove the RTL8231 GPIO controller node from this base file
since the chip might not be found in all Realtek RTL839x devices.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Replace the interrupt controller node with the new realtek,rtl-intc
node and change all device interrupts to use the 2 field notation:
interrupts = <[SoC IRQ] [Index to MIPS IRQ]>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order to support VSMP, enable support for both VPEs
of the RTL839X and RTL930X SoCs in the irq-realtek-rtl
driver. Add support for IRQ affinity setting.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
In order for the Platform includes to be available on
all sub-targets, make them dependent on CONFIG_RTL83XX.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL838X SoCs do not use Aquantia PHYs, remove this.
Also the RTL838X uses a high resolution R4K timer.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Creates RTL83XX as a basic kernel config parameter for the
RTL838X, RTL839x, RTL930X and RTL931X platforms with respective
configurations for the SoCs, which are introduced in addition.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Create the RTL838x specific Makefiles. Move CPU-type into
rtl838x.mk as this is specifc to that platform. Add
rtl838x subtarget into main Makefile.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
mv generic/target.mk to rtl838x/target.mk in order to create
an initial makefile for the rtl838x sub-architecture
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The EEPROMs on SFP modules are compatible both to I2C as well
as SMBus. However, the kernel so far only supports I2C
access. We add SMBus access routines, because the I2C driver
for the RTL9300 HW only supports that protocol. At the same
time we disable I2C access to PHYs on SFP modules as otherwise
detection of any SFP module would fail. This is not in any
way problematic at this point in time since the RTL93XX
platform so far does not support PHYs on SFP modules.
The patches are copied and rebased version of:
https://bootlin.com/blog/sfp-modules-on-a-board-running-linux/
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C
masters, each with a fixed SCL pin, that cannot be changed. Each of these
masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA.
This multiplexer directly controls the two masters and their shared
IO configuration registers to allow multiplexing between any of these
busses. The two masters cannot be used in parallel as the multiplex
is protected by a standard multiplex lock.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This adds support for the RTL9300 and RTL9310 I2C controller.
The controller implements the SMBus protocol for SMBus transfers
over an I2C bus. The driver supports selecting one of the 2 possible
SCL pins and any of the 8 possible SDA pins. Bus speeds of
100kHz (standard speed) and 400kHz (high speed I2C) are supported.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This patch removes support for the legacy GPIO driver, since now
the gpio-otto driver can be used on all platforms
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
We add support for the RTL930X and RTL931X architectures
in the gpio-realtek-otto.c driver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Drop patches and files for Linux 5.4 now that we've been using 5.10
for a while and support for Linux 5.4 has gone out-of-sync.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The bit position mask was accidentally made too wide, overlapping with the LSB
from the byte position mask. This caused ECC calculation to fail for odd bytes
Signed-off-by: Chad Monroe <chad.monroe@smartrg.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
flowtable->net was initialized too late, and this could be triggered even
without hardware offload support on the device
Signed-off-by: Felix Fietkau <nbd@nbd.name>
It's reported that current memory detection code occasionally detects
larger memory under some bootloaders.
Current memory detection code tests whether address space wraps around
on KSEG0, which is unreliable because it's cached.
Rewrite memory size detection to perform the same test on KSEG1 instead.
While at it, this patch also does the following two things:
1. use a fixed pattern instead of a random function pointer as the magic
value.
2. add an additional memory write and a second comparison as part of the
test to prevent possible smaller memory detection result due to
leftover values in memory.
Fixes: 6d91ddf517 ("ramips: mt7621: add support for memory detection")
Reported-by: Rui Salvaterra <rsalvaterra@gmail.com>
Tested-by: Rui Salvaterra <rsalvaterra@gmail.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
The issue of EAP frames sent to group address (or the wrong address) has been
addressed in mac80211, so this hack is no longer needed
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This caches flows between MAC addresses on separate ports, including their VLAN
in order to bypass the normal bridge forwarding code.
In my test on MT7622, this reduces LAN->WLAN bridging CPU usage by 6-10%,
potentially even more on weaker platforms
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Had to update generic defconfig (make kernel_menuconfig CONFIG_TARGET=generic)
for this bump, but since that only modifies the target defined in .config,
and since that target also needed to be updated for unrelated reasons, manually
propagated the newly added symbol to the generic config.
Removed upstreamed:
pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch[1]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.99&id=080f371d984e8039c66db87f3c54804b0d172329
Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200
Signed-off-by: John Audia <graysky@archlinux.us>
The locations of MAC addresses in mtd for LAN/WAN on ELECOM WRC-2533GS2
are changed from the other WRC-GS/GST devices with 2x PCIe. So move the
related configurations in mt7621_elecom_wrc-gs-2pci.dtsi to dts of each
model.
- WRC-1750GS
- WRC-1750GSV
- WRC-1750GST2
- WRC-1900GST
- WRC-2533GST
- WRC-2533GST2
-> LAN: 0xE000, WAN: 0xE006
- WRC-2533GS2
-> LAN: 0xFFF4, WAN: 0xFFFA
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Reported MAC addresses:
| interface | MAC address | source | comment
|-----------|-------------------|----------------|---------
| LAN | 90:xx:xx:18:xx:1F | | [1]
| WAN | 90:xx:xx:18:xx:1D | |
| WLAN 2G | 92:xx:xx:48:xx:1C | |
| WLAN 5G | 90:xx:xx:18:xx:1C | factory 0x4 |
| | 90:xx:xx:18:xx:1C | config ethaddr |
[1] Used in this patch as WLAN 2G MAC address with the local bit set
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
ipTIME AX2004M is an 802.11ax (Wi-Fi 6) router, based on MediaTek
MT7621A.
Specifications:
* SoC: MT7621A
* RAM: 256 MiB
* Flash: NAND 128 MiB
* Wi-Fi:
* MT7915D: 2.4/5 GHz (DBDC)
* Ethernet: 5x 1GbE
* Switch: SoC built-in
* USB: 1x 3.0
* UART: J4 (115200 baud)
* Pinout: [3V3] (TXD) (RXD) (GND)
MAC addresses:
| interface | MAC address | source | comment
|-----------|-------------------|----------------|---------
| LAN | 58:xx:xx:00:xx:9B | | [1]
| WAN | 58:xx:xx:00:xx:99 | |
| WLAN 2G | 58:xx:xx:00:xx:98 | factory 0x4 |
| WLAN 5G | 5A:xx:xx:40:xx:98 | |
| | 58:xx:xx:00:xx:98 | config ethaddr |
[1] Used in this patch as WLAN 5G MAC address with the local bit set
Load addresses:
* stock
* 0x80010000: FIT image
* 0x81001000: kernel image -> entry
* OpenWrt
* 0x80010000: FIT image
* 0x82000000: uncompressed kernel+relocate image
* 0x80001000: relocated kernel image -> entry
Notes:
* This device has a dual-boot partition scheme, but this firmware works
only on boot partition 1. The stock web interface will flash only on the
inactive boot partition, but the recovery web page will always flash on
boot partition 1.
Installation via recovery mode:
1. Press reset button, power up the device, wait >10s for CPU LED
to stop blinking.
2. Upload recovery image through the recovery web page at 192.168.0.1.
Revert to stock firmware:
1. Install stock image via recovery mode.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Turns out the MT7531 switch IRQ line is connected to GPIO#53 just like
on the BPi-R64, so this seems to be part of the reference design and
will probably apply to most MT7622+MT7531 boards.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Now that we support link-state-change interrupts, wire up MT7531 IRQ
line which is connected to GPIO#53 according to the schematics [1].
As a result, PHY state no longer needs to be polled on that board.
[1]: https://forum.banana-pi.org/t/bpi-r64-mt7622-schematic-diagram-public/10118
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Support MT7530 PHY link change interrupts, and enable for MT7621.
For external MT7530, a GPIO IRQ line is required, which is
board-specific, so it should be added to each DTS. In case the
interrupt-controller property is missing, it will fall back to
polling mode.
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Add support for MediaTek Gigabit Ethernet PHYs found in MT7530 and
MT7531. Fix some link up/down issues.
The errornous check for the PHY mode which broke things with MT7531
has been removed as suggested by patch
net: phy: mediatek: remove PHY mode check on MT7531
As a result, things are working fine now on MT7622+MT7531 as well.
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
The kernel configuration allows us to select a default qdisc. Let's do this for
5.10 (as 5.4 is on its way out) and get rid of the hacky patch we've been
carrying.
Acked-by: Jo-Philipp Wich <jo@mein.io>
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
