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3 Commits

Author SHA1 Message Date
Felix Fietkau
0b296d3808 ar71xx: use correct PLL configuration register bitmask for QCA956x SoC. 
Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47363
 2015-11-02 18:20:51 +00:00
John Crispin
c9426352ce ar71xx: fix ath79_soc_rev value for QCA9531 ver. 2 
ath9k expects to get revision id 2 for the QCA9531 ver. 2 rev. 0. This
fixes the very low TX power on some devices like the TP-LINK
TL-WR841ND v10.

As ath79_soc_rev is only used to get the revision number to ath9k on the
QCA9533, just set it to the expected value on the ver. 2.

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Tested-by: Felix Kaechele <felix@kaechele.ca>

SVN-Revision: 47262
 2015-10-26 09:01:34 +00:00
Felix Fietkau
b704d3c96e ar71xx: reorganize 4.1 patch directory layout 
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 46430
 2015-07-19 17:59:08 +00:00