Commit Graph

13 Commits

Author SHA1 Message Date
Shiji Yang
731318667d ath79: correct dts ngpios properties
SoC Model	GPIO number

ar7100		12
ar7240		18(unknown, default)
ar7241		20
ar7242		18
ar9132		22(unknown, default)
ar9331		30
ar934x		23
qca953x		18
qca955x		24
qca956x		23

Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Link: https://github.com/openwrt/openwrt/pull/15784
Signed-off-by: Robert Marko <robimarko@gmail.com>
2024-07-04 19:30:37 +02:00
Rosen Penev
b07b8aade7
ath79: rename pcie-controller to pcie
pcie-controller was renamed to pcie since at least kernel 4.14. Match it
here to get rid of dtc warnings.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
2024-01-05 16:17:57 +01:00
Shiji Yang
520c90854c ath79: move reference clock node to SoC dtsi
AR7161, AR724x, AR9132 and QCA95xx only support fixed frequency external
crystal oscillator, so move reference clock node to SoC dtsi files.

Signed-off-by: Shiji Yang <yangshiji66@qq.com>
2022-11-09 22:55:33 +01:00
David Bauer
0494278073 ath79: resolve GPIO address conflicts
The ar71xx GPIO driver only uses 0x24 registers, all following GPIO
registers are using to control pinmux functions, which are not handles
by the GPIO driver but the generic Linux pinctrl driver.

For some SoC conflicting address ranges were defined for these (AR7240 &
AR9330).

Resolve these cases and align the address space of the GPIO controller
between all SoCs, as the used address space of the driver is identical
for all these.

Signed-off-by: David Bauer <mail@david-bauer.net>
2021-07-01 23:26:49 +02:00
Adrian Schmutzler
3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00
David Bauer
da55758cc5 ath79: specify device-type for PCI controllers
Specify the device_type property for PCI as well as PCIe controllers.
Otherwise, the PCI range parser will not be selected when using kernel
5.10.

Signed-off-by: David Bauer <mail@david-bauer.net>
2021-02-20 01:26:14 +01:00
Adrian Schmutzler
3ca2d31c54 ath79: move ath79-clk.h include to ath79.dtsi
ath79.dtsi uses ATH79_CLK_MDIO, so the include

  <dt-bindings/clock/ath79-clk.h>

needs to be moved there.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-09-25 23:24:09 +02:00
David Bauer
d883eaacd4 ath79: add QCA9550 reset sequence
The QCA9550 family of SoCs have a slightly different reset
sequence compared to older chips.

Normally the bootloader performs this sequence, however
some bootloader implementation expect the operating system
to clear the reset. Also get the PCIe resets from OF to
support the second RC of the QCA9558.

This is required for the AVM FRITZ!WLAN Repeater 1750E to work,
as EVA leaves the PCIe bus in reset.

Tested: AVM FRITZ!WLAN Repeater 1750E - OCEDO Koala

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-04-17 13:23:06 +02:00
Michal Cieslakiewicz
69df7eb73d ath79: add LAN LEDs control bits for AR724x GPIO function pinmux
Currently AR724x pinmux for register 0x18040028 controls only JTAG disable bit.
This patch adds new DTS settings to control LAN LEDs and CLKs that allow
full software control over these diodes - exactly the same is done by ar71xx
target in device setup phase for many routers (WNR2000v3 for example).

'switch_led_disable_pins' clears AR724X_GPIO_FUNC_ETH_SWITCH_LED[0-4]_EN bits.
'clks_disable_pins' clears AR724X_GPIO_FUNC_CLK_OBS[1-5]_EN and
AR724X_GPIO_FUNC_GE0_MII_CLK_EN bits. These all should be used together, along
with 'jtag_disable_pins', to allow OS to control all GPIO-connected LEDs and
buttons on device.

Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
2019-10-21 13:14:52 +02:00
Alex Maclean
fab3254b32 ath79: add pinmux node to ar724x.dtsi
Signed-off-by: Alex Maclean <monkeh@monkeh.net>
2018-06-01 08:23:02 +02:00
Mathias Kresin
bc04cf780e ath79: ar724x: fix pll settings
Add the syscon compatible, otherwise used functions like
syscon_regmap_lookup_by_phandle() will return an error and setting the
ethernet pll data wont work at all.

Fix the pll register width. Writing to registers out of the range via
syscon isn't possible and returns an error. On ar7242 the last pll
register - Current Audio Modulation Logic Output - is at 0x1805003c.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-05-17 07:40:19 +02:00
Rafał Miłecki
66c8afd115 ath79: relicense DTS files to the GPL 2.0+ / MIT
Some maintainers prefer DTS files licensed under permissive license like
MIT / BSD. As all DT bindings should be OS independent and DTS files are
pretty separated from Linux code it probably makes sense to share them
across projects.

The safest solution is to use dual licensing: that way it stays clear
these files can be used in GPL projects without depending on current
belief of licenses compatibility.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: John Crispin <john@phrozen.org>
2018-05-07 10:31:35 +02:00
John Crispin
53c474abbd ath79: add new OF only target for QCA MIPS silicon
This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.

Signed-off-by: John Crispin <john@phrozen.org>
2018-05-07 08:06:51 +02:00