Commit Graph

536 Commits

Author SHA1 Message Date
Goetz Goerisch
3774f3272e treewide: rename ZyXEL to Zyxel
The company Zyxel rebranded some years ago.
Currently the casing is according to the old branding even
for newer devices which already use the new branding.

This commit aligns the casing of Zyxel everywhere.

Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15652
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2024-08-25 15:08:25 +02:00
Kevin Jilissen
5a5c52085a realtek: Trap LLDP packets to the CPU
We should setup the registers for trapping LLDP packets to the CPU.
Currently, these packets are forwarded to all ports which is not desired
behaviour.

Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
2024-05-10 16:03:51 +02:00
Kevin Jilissen
81ab9ef2d1 realtek: Change LLTP register to LLDP
These registers control the handling of Link Layer Discovery Protocol
(LLDP) packets. This seems to be a typo in the naming.

Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
2024-05-10 16:03:51 +02:00
Stijn Tintel
a9781a04a1 realtek: add RTL821X_CHIP_ID
According to the Realtek SDK code, the RTL8214FC, RTL8218B and RTL8218FB
all have the same chip ID 0x6276. Let's add a constant for it, as we're
using it in more than one location.

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
2024-05-07 12:27:33 +03:00
Stijn Tintel
1626b06683 realtek/rtl839x: respect phy-is-integrated property
Respect the phy-is-integrated property on ethernet-phy nodes.

There are RTL8393M switches where the PHYs at address 48 and 49 are
provided by an external RTL8214FC. Hardcoding them to use the internal
SerDes makes it impossible to use the ports connected to such an
external PHY. Respect the phy-is-integrated property on ethernet-phy
nodes as a first step to support such ports.

The potential impact for this should be limited to RTL8393 based
switches, and looking at the commit messages and device tree files of
the supported switches based on this SoC, the SFP and/or combo ports are
either not working (D-Link DGS-1210-52, Netgear GS750E, TP-Link
SG2452P/T1600G-52PS), use PHYs at a different address (Panasonic
SwitchM48EG PN28480K), or already have the phy-is-integrated property
set on the PHYs at address 48 and 49.

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Daniel Golle <daniel@makrotopia.org>
2024-05-07 12:27:30 +03:00
Hauke Mehrtens
9693ed6a9e kernel: bump 5.15 to 5.15.155
Manual adapted the following patches:
   generic/hack-5.15/221-module_exports.patch
   octeontx/patches-5.15/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2024-04-16 23:11:25 +02:00
Stijn Tintel
291efaf765 realtek: fix filter_port_list_reverse calls
The function introduced in commit 7cbfe5654d is named
filter_port_list_reverse, not filter_port_list_reversed.

Fixes the following error on hpe,1920-8g-poe-65w and
hpe,1920-8g-poe-180w.

  /bin/board_detect: /etc/board.d/02_network: line 84: filter_port_list_reversed: not found

Fixes: 7cbfe5654d ("realtek: move port filtering out of uci_set_poe()")
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Sander Vanheule <sander@svanheule.net>
2024-04-13 13:22:11 +03:00
Mirko Vogt
0688cf5aeb realtek: add support for switch Zyxel GS1900-24EP
This device is very similar to the GS1900-24E switch (added in b515ad1),
except that the first 12 of 24 ethernet ports are capable of PoE and the
physical jacks are in the right order - unlike for the GS1900-24E, where
even and uneven ports are flipped (up <-> down on panel).

Zyxel version code for this device (-24EP) is: ABTO

Signed-off-by: Mirko Vogt <mirko-openwrt@nanl.de>
2024-04-08 21:31:55 +02:00
Goetz Goerisch
71ccb35017 realtek: add Zyxel GS1900-8 v2
The Zyxel GS1900-8 v2 or Rev.B1 is a newer variant of the GS1900-8, but
otherwise similar to the other GS1900 switches.

Differences
------------
* Front Button labeled RESTORE
* NO Power Switch on rear
* Serial Header next to the barrel power connector
* Part Number ends 0102F

Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
2024-03-25 21:28:44 +01:00
Richard Kunze
92c21b2e18 realtek: support common GPIOs on D-Link DGS-1210-16
D-Link DGS-1210-16 hangs when rebooting and has no support for the reset
button.

Fix both by enabling the same GPIOs for reboot and the reset button as
already used for D-Link DGS-1210-20 and D-Link DGS-1210-28.

Signed-off-by: Richard Kunze <kunze@tivano.de>
2024-03-23 18:36:51 +01:00
Bjørn Mork
6da308f4de realtek: fix Netgear GS110TPP OEM install
Recent OEM firmware versions test the version number embedded in the uimage
"name" header field. The exact restricton is unknown, but "7.0.8.4" seems
to be the lowest number accepted on a GS110TPPv1 which already has that
version or higher.

A "9.9.9.9" version is accepted as valid by the GS110TPPv1 OEM firmware,
and considered both unique enough to identify an OpenWrt image and
moderately future proof against OEM version bumps.

This change is also boot tested on a GS108Tv3 with

 "BOOT Loader Version 1.0.0.2 (2018-08-31 17:05:26 UTC)"

to verify that it doesn't break boot on older hardware.

Link: https://forum.openwrt.org/t/72510/58
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2024-02-18 09:56:45 +01:00
Sander Vanheule
6f83a708c8 base-files: move uci_set_poe() to uci-defaults.sh
PoE devices in the realtek target have the possibility to add PSE info
to the board description via 02_network. Make this available for all
targets, by moving the uci_set_poe() function to the globally available
uci-default.sh script.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2024-02-12 20:46:51 +01:00
Sander Vanheule
7cbfe5654d realtek: move port filtering out of uci_set_poe()
uci_set_poe() now performs two duties: filtering the list of device
ports to exclude non-PoE ports, and generating the PoE related device
config.

Extract the port filtering to an external function, which is made a bit
more readable by the use of 'sort -V [-r] | uniq -u' to filter duplicate
entries out of a (reverse) version sorted list.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2024-02-12 20:46:51 +01:00
Tobias Schramm
356a0b86eb realtek: add support for chassis fan on ZyXEL XGS1250-12
The ZyXEL XGS1250-12 has a chassis fan. The fan is positioned perfectly to
provide additional cooling to the Aquantia NBase-T phys. Testing has shown
that the phys can reach temperatures upwards of 72 degrees Celsius quite
easily at about 20 degrees Celsius ambient.
Support the chassis fan to give the phys a bit of extra cooling.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2024-02-12 20:09:24 +01:00
Christian Marangi
db9f26cfcb
realtek: convert to new LED color/function format where possible
Initial conversion to new LED color/function format
and drop label format where possible. The same label
is composed at runtime.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-02-07 14:48:44 +01:00
Christian Marangi
f038c0c18f
realtek: drop redundant label with new LED color/function format
Drop redundant label with new LED color/function format declared.
This was needed previously when the new format wasn't supported by
leds.sh functions script. Now that is supported this property
can be removed in favor of the new format.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-02-07 14:48:44 +01:00
Tobias Schramm
af9bf9a949 realtek: enable in-band configuration of SFP port on ZyXEL XGS1250-12
The rtl93xx SoC supports both 1000Base-X and 10GBase-CR on its SerDes
interfaces. Enable dynamic switching between mac-signaled modes to
support 1000Base-X and 10GBase-CR on the SFP port.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2024-02-05 20:44:46 +01:00
Tobias Schramm
9daf4dff6b realtek: 5.15: rtl93xx: add 1000Base-X and 10GBase-CR support on SerDes
This patch adds support for 1000Base-X and 10GBase-CR directly on the
SerDes lanes of rtl93xx SoCs.
This fixes SFP/SFP+ support on devices like the XSG1250-12.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2024-02-05 20:44:46 +01:00
Tobias Schramm
9fe2412e62 realtek: 5.15: rtl930x: introduce SerDes mode macros
Previously SerDes modes were specified ad-hoc in hex. Introduce and use
macros for SerDes modes.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2024-02-05 20:44:46 +01:00
Tobias Schramm
2f8a881895 realtek: 5.15: rtl93xx: fix switch/case indentation
Small stylistic fixup, one switch case statement was incorrectly indented.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2024-02-05 20:44:46 +01:00
Tobias Schramm
9b066384f9 realtek: 5.15: rtl93xx: remove unused SerDes mode selection
rtl93xx_phylink_mac_config used to determine sds_mode without ever using
it. Drop that code.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2024-02-05 20:44:46 +01:00
Tobias Schramm
0ac785caf3 realtek: 5.15: rtl930x: fix SerDes phy register write
The indirect SerDes phy register write function was missing the actual
write call. Add it.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2024-02-05 20:44:46 +01:00
Stijn Segers
557db5106c realtek: fix zyxel-vers usage for XGS1250-12
Commit daefc646e6 ("realtek: fix ZyXEL initramfs image generation")
fixed a shell expansion issue with zyxel-vers usage. Commit 045baca10b
("realtek: deduplicate GS1900 recipes") took care of this for the
rtl838x and rtl839x subtargets, but the single device officially
supported in rtl930x - the XGS1250-12 - was overlooked. This commit
updates the XGS1250-12 build recipe as well.

Signed-off-by: Stijn Segers <foss@volatilesystems.org>
2024-02-04 13:31:35 +01:00
Christian Marangi
1b3259eb5c generic: 5.15: backport upstream Aquantia PHY firmware loader patches
Backport merged upstream patch that adds support for firmware loader
from NVMEM or attached filesystem for Aquantia PHYs.

Refresh all kernel patches affected by this change.

Also update the path for aquantia .ko that got moved to dedicated
directory upstream.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
[rmilecki: port to 5.15]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
2024-01-26 17:52:24 +01:00
Christian Marangi
0f09fd60fb
realtek: 5.15: refresh HSGMII patch due to recent PHY backport
Refresh HSGMII patch due to recent PHY backport that cause
compilation warning for case not handled in phy_interface_num_ports.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-01-26 15:50:43 +01:00
Rafał Miłecki
2df8a0ccb0 kernel: 5.15: backport v6.1 PHY changes required for Aquantia
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
2024-01-26 11:48:50 +01:00
Michel Thill
135e107620 realtek: d-link dgs-1210-10p improve sfp support
The current dts file of dgs-1210-10p doesn't support link states
for the sfp ports (they are always up).
This patch tries to give better support for this and was run tested
on dgs-1210-10p.

It was heavily inspired from Paul Fertser, RaylynnKnight
and the author of dgs-1210-10mp-f.dts

https://forum.openwrt.org/t/dlink-dgs-1210-10p-with-glc-t-co-sfp/170928

Signed-off-by: Michel Thill <jmthill@gmail.com>
2024-01-23 10:57:06 +01:00
Peter Körner
5798e12e4a
rtl838x: debugfs use constants from mach-rtl83xx.h
The register constants were duplicated in net/dsa/rtl83xx/debugfs.c and asm
mach-rtl838x/mach-rtl83xx.h. This commit removes this duplication.

Signed-off-by: Peter Körner <git@mazdermind.de>
2024-01-15 18:09:22 +01:00
Peter Körner
668a049171
rtl838x: fix RTL838X_LED_SW_CTRL definition
According to https://svanheule.net/realtek/maple/register/led_sw_ctrl and also
drivers/net/dsa/rtl83xx/debugfs.c LED_SW_CTRL on the RTL838X should be 0xa00c
not 0x0128. Please note, that is is 0x0128 on the RTL8390/cypress SOC family.

Signed-off-by: Peter Körner <git@mazdermind.de>
2024-01-15 18:09:22 +01:00
Peter Körner
b49a0feb20
rtl931x: reformat broken indentation
the given code-format did not correctly express the condition and made the code
harder to read then necessary.

Signed-off-by: Peter Körner <git@mazdermind.de>
2024-01-15 18:09:19 +01:00
Jacob Potter
735efbfb7c realtek: rtl838x: add Netgear GS110TUP v1 support
The GS110TUP v1 is a managed switch similar to the GS110TPP v1, but with
port 10 as SFP instead of RJ-45 and a total budget of 240 watts. Ports
1-4 support 60-watt 802.3bt PoE and ports 5-8 support 30-watt 802.3at.

The flash layout of the two switches are identical, and the U-Boot
configurations are the same except for having a different magic number,
so installation can be done via the same U-Boot method.

The following command will be needed to enable the port LEDs as per
https://forum.openwrt.org/t/72510/51 :
    fw_setenv bootcmd "rtk network on; boota"

Additionally, port 9 (1000base-T from a separate QSGMII PHY) does not
function without this. Port 10 was not tested as no SFP module was
available.

Signed-off-by: Jacob Potter <jacob@j4cbo.com>
[rebase on merged flash layout]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2024-01-13 16:45:05 +01:00
Sander Vanheule
92e0baba42 realtek: rtl838x: join Netgear GSxxx flash layouts
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.

Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2024-01-13 16:45:05 +01:00
Harshal Gohel
e691e2b302 rtl83xx: dsa: reset PVID to 1 instead of 0
Before, PVID is reset for all ports and goes out of bounds. Also, PVID
is later changed by dsa configuration by `ip link` and `bridge vlan`
commands, this does not change the CPU port PVID and CPU PVID stays 0.
It does not allow sending packets from OpenWrt to any connected devices
unless default configuration is changed

This change iterates up to and including cpu_port and sets default PVID
to 1. For lan* ports PVID can be configured with `ip link` and `bridge
vlan` commands

Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
2024-01-09 21:20:37 +01:00
Harshal Gohel
da495c477d rtl93xx: dsa: Fix 802.1QinQ for trunk ports
Fix incorrect register value being set for VLAN_PORT_FWD

Before, the 0b1111 would be set for the register which means outgoing
packets would receive an extra tag, corresponding to the PVID of the
port.

On untagged ports, this meant outgoing packets with a single tag.

On tagged ports, this meant outgoing QinQ packets, where the inner tag
was either the PVID of the untagged ingress port, or the already
assigned original (single) tag.

Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
2024-01-09 21:19:41 +01:00
Harshal Gohel
fe01435b69 rtl83xx: dsa: Clear duplex bit correctly
Without this, luci shows 10M full duplex when there is no link. So
explicitly set half duplex and unknown speed.

Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
2024-01-09 21:19:21 +01:00
Harshal Gohel
2cfb1ecf10 rtl930x: Rework per port LED configuration
Use led_setX to determine number of LEDs per port. Introduce macros to
calculate register value and shift for particular LED in a particular
set.

Problem with previous implementation is that it uses is10G status to
determine leds per port. However with usxgmii, driver sets 10g, 5g and
2.5g so even though there are only 2 leds per port it selects 4 leds per
port

This implementation relies on configured led_set node.

Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
2024-01-09 21:18:50 +01:00
Harshal Gohel
a376508216 rtl83xx: dsa: Do nothing when vid 0
Following other dsa drivers, vid 0 is no-op

Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
2024-01-09 21:18:46 +01:00
Harshal Gohel
e0c0137eed rtl83xx: dsa: disable VLAN filtering on CPU port
Before driver code
 - enabled egress filter for cpu and non-cpu ports
 - enabled ingress filter for non-cpu ports

This patch explicitly enables ingress and egress filtering for non-cpu
ports and disables ingress and egress filtering for cpu port.

Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
2024-01-09 21:15:37 +01:00
Harshal Gohel
3e753c45cd rtl838x: Enable jumbo frames by default
Increase DEFAULT_MTU and max-mtu size
Increase truncate length on rx of jumbo frame

Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
2024-01-09 21:15:23 +01:00
Michael 'ASAP' Weinrich
f1de1a090f realtek: correct typo in port numbering
Port 10 was incorrectly labelled as nonexistent port 0.

Signed-off-by: Michael 'ASAP' Weinrich <michael@a5ap.net>
2024-01-05 20:21:45 +01:00
Michael 'ASAP' Weinrich
3acd584361 realtek: fix network connectivity on GS750E
Currently OpenWRT does not know how to properly reset the network switch. This would result in
a switch that seemed to come up properly but was unable to handle any traffic. Presumably something
earlier in the boot chain is configuring a part of the switch that gets wiped out when its reset.

For now comment out the reset GPIO entry in the device tree until the driver better supports
bringing up the switch after a reset.

Signed-off-by: Michael 'ASAP' Weinrich <michael@a5ap.net>
2024-01-05 20:21:45 +01:00
Rosen Penev
89ff407d68
treewide: use ethtool_puts instead of memcpy
The former is a safer and more readable version.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
2024-01-05 16:12:49 +01:00
Pascal Ernster
4e8c9cebe5 realtek: Use hex for "soc" identifier in debugfs
The upper 16 bits of the 32 bit value encode the SoC model in BCD
notation (for example 0x83806800 on a Netgear GS108Tv3 with an
RTL8380M), so it makes more sense to output the value in hex notation
than in decimal notation.

Signed-off-by: Pascal Ernster <git@hardfalcon.net>
2023-12-31 14:13:43 +01:00
Rosen Penev
1fa705dbec realtek: fix addresses in DT node names
Mostly wrong address format, one missing address, and one spurious
address suffix.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2023-12-30 11:53:47 +01:00
Tobias Schramm
8b706d9297 realtek: 5.15: rtl93xx: support 100BASE-T and 10BASE-T MAC modes
The MAC embedded in rtl93xx switch SoCs needs different mac mode bits set
to support 10BaseT and 100BaseT link modes. Set them accordingly.

This change has been tested on a ZyXEL XGS1250-12.

Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
2023-12-24 01:36:39 +01:00
John Audia
bcb37c84d2 kernel: bump 5.15 to 5.15.143
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.143

Removed upstreamed:
	generic/backport-5.15/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch[1]

Manually rebased:
        mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.143&id=00beca907a7be61da935bb687f9601420fc5f8a8

Build system: x86_64
Build-tested: ramips/tplink_archer-a6-v3
Run-tested: ramips/tplink_archer-a6-v3

Signed-off-by: John Audia <therealgraysky@proton.me>
2023-12-19 14:18:55 +01:00
Raylynn Knight
daba89bca3 realtek: Clean up and standardize realtek-poe support
This patch cleans up and standardizes realtek-poe support for realtek
based switches that have supported PoE ports.

The power output of switches supported by realtek-poe package can be
configured in the 02_network ucidef_set_poe() function.  This was missed
when some PoE capable switches supported by realtek-poe were added.

The realtek-poe package at one point replaced a lua-rs232 based script
and some devices were not updated to use the realtek-poe package.
Consistently add realtek-poe package to DEVICE_PACKAGES for switches
with supported PoE.

Signed-off-by: Raylynn Knight <rayknight@me.com>
2023-12-13 20:10:23 +01:00
John Audia
6c118efc01 kernel: bump 5.15 to 5.15.140
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.140

Removed upstreamed:
	mvebu/patches-5.15/106-Revert-i2c-pxa-move-to-generic-GPIO-recovery.patch[1]

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.140&id=06d320ca170b4e59bb261e2ce3ffe84e9154d42b

Build system: x86_64
Build-tested: ramips/tplink_archer-a6-v3
Run-tested: ramips/tplink_archer-a6-v3

Signed-off-by: John Audia <therealgraysky@proton.me>
2023-11-29 23:41:33 +01:00
Rosen Penev
d1b5981038
realtek: convert to nvmem-layout
nvmem-cells is deprecated.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
2023-11-24 16:37:02 +01:00
Andreas Böhler
fd0aaf93d1 realtek: add support for TP-Link T1600G-28TS v3
This is an RTL8382-based switch with 24 copper ports + 4 SFP ports

Specifications:
---------------
 * SoC:       Realtek RTL8382M
 * Flash:     32 MiB SPI flash
 * RAM:       256 MiB
 * Ethernet:  24x 10/100/1000 Mbps
 * Buttons:   1x "Reset" button
 * UART:      1x serial header, unpopulated
 * SFP:       4 SFP ports

Works:
------
  - (24) RJ-45 ethernet ports
  - Switch functions
  - Buttons
  - Sys LED on front panel (no port LEDs)

Not yet enabled:
----------------
  - Port LEDs (no driver for RTL8231 in this mode)
  - SFP cages (no driver for PHY)

Install via web interface:
-------------------------

Not supported at this time.

Install via serial console/tftp:
--------------------------------

The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U6)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as soon as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWRT.

Blind install via tftp:
-----------------------

This method works when it's not feasible to install a serial header.

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"
 3. Watch network traffic (tcpdump or wireshark works)
 4. Power on the device.
 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
 6. When 192.168.0.30 makes tftp requests, release pin 16
 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2023-10-20 18:13:57 +02:00