Apply the same approach as in commit 3b53d6fdbc ("ar71xx: fix pci irq
init on kernel 4.14") to fix IRQ initialization for ath79-based chipsets
on rb4xx.
Ref: PR#2182
Acked-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Signed-off-by: W. Michael Petullo <mike@flyn.org>
[commit ref fix]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
(cherry picked from commit 8c7d6c47a7)
Remove references to broken and mostly deprecated phy_ethtool_ioctl, use
new {s,g}et_link_ksettings and add nway_reset which was previously
handled in phy_ethtool_ioctl.
Cc: John Crispin <john@phrozen.org>
Ref: https://bugs.openwrt.org/index.php?do=details&task_id=1982
Signed-off-by: Petr Štetiar <ynezz@true.cz>
This ioctl is currently routed through generic interface code:
dev_ioctl
dev_ethtool
__ethtool_get_link_ksettings
phy_ethtool_ioctl
Cc: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
The vendor firmware only uses two mac addresses, the mac address on the
label and the label + 1. While checking multiple devices, all labels have
even mac addresses. Concluding only 2 address are assigned to a device.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
It was reported, that latest ar71xx builds have broken networking on
TP-Link TL-WPA8630 and Nanostation M5 XW devices and that by reverting
the offending commit, everything is back to normal.
Fixes: d3506d1 ("ar71xx: ag71xx: fix compile error when enabling debug")
Signed-off-by: Petr Štetiar <ynezz@true.cz>
CPU: AR9342 SoC
RAM: 64 MB DDR2
Flash: 8 MB NOR SPI
Ports: 100 MBit (24V PoE in)
WLAN: 2.4/5 GHz
UART: 1 UART on PCB marked as J1 with 115200 8N1 config
LEDs: Power, Ethernet, 4x RSSI LEDs (orange, red, 2x green)
Buttons: Reset
UART connection details
.---------------------------------.
| |
[ETH] J1 [ANT]
| o VCC o RX o TX o GND |
`---------------------------------'
Flashing instructions using recovery method over TFTP
1. Unplug the ethernet cable from the router.
2. Using paper clip press and hold the router's reset button. Make sure
you can feel it depressed by the paper clip. Do not release the button
until step 4.
3. While keeping the reset button pressed in, plug the ethernet cable
back into the AP. Keep the reset button depressed until you see the
device's LEDs flashing in upgrade mode (alternating LED1/LED3 and
LED2/LED4), this may take up to 25 seconds.
4. You may release the reset button, now the device should be in TFTP
transfer mode.
5. Set a static IP on your Computer's NIC. A static IP of 192.168.1.25/24
should work.
6. Plug the PoE injector's LAN cable directly to your computer.
7. Start tftp client and issue following commands:
tftp> binary
tftp> connect 192.168.1.20
tftp> put openwrt-ar71xx-generic-ubnt-bullet-m-xw-squashfs-factory.bin
Tested only on Bullet M2HP.
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Looks identical to the v2.
This PR adds support for a popular low-cost 2.4GHz N based AP
Specifications:
- SoC: Qualcomm Atheros QCA9533 (650MHz)
- RAM: 64MB
- Storage: 8 MB SPI NOR
- Wireless: 2.4GHz N based built into SoC 2x2
- Ethernet: 1x 100/10 Mbps, integrated into SoC, 24V POE IN
Installation:
Flash factory image through stock firmware WEB UI
or through TFTP
To get to TFTP recovery just hold reset button while powering on for
around 4-5 seconds and release.
Rename factory image to recovery.bin
Stock TFTP server IP:192.168.0.100
Stock device TFTP adress:192.168.0.254
Tested-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Robert Marko <robimarko@gmail.com>
[Rebased, adjusted for separate tplink-safeloader entry, dynamic partitioning]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
The Mikrotik RouterBOARD SXT 2nD r3 is an outdoor WiFi AP / CPE
with a single 2.4 GHz radio and a 100 Mbps Ethernet port.
The device similar to the SXT 2nD r2, but it has SPI NOR flash instead
of NAND flash.
Hardware
--------
CPU: Atheros AR9344 (600 MHz)
RAM: 64 MiB
FLASH: 16 MiB SPI NOR W25Q128
ETH: 1x 100 Mbps Atheros AG71xx
WiFi: 2T2R 802.11b/g/n (ath9k)
Power: Passive PoE 8-30 V
Installation instructions:
1. Boot openwrt-ar71xx-mikrotik-vmlinux-initramfs.elf using a
DHCP+TFTP server.
2. Erase the "firmware" partition using the mtd command. This should
no longer be required once this patch is merged.
3. Use sysupgrade to install to flash. The file
openwrt-ar71xx-mikrotik-rb-nor-flash-16M-squashfs-sysupgrade.bin
should be used.
Signed-off-by: Xavier Douville <github@douville.org>
fixes intermittent loss of connectivity on 1Gbit port, with
log message:
803x_aneg_done: SGMII link is not ok
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Starting from kernel 4.5, phy_id needs to be fetched from a different location.
not doing so results in this compile error:
drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c: In function 'ag71xx_phy_connect_multi':
drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c:133:35: error: 'struct mdio_device' has no member named 'phy_id'
ag->mii_bus->mdio_map[phy_addr]->phy_id);
^
./include/linux/printk.h:137:18: note: in definition of macro 'no_printk'
printk(fmt, ##__VA_ARGS__); \
^~~~~~~~~~~
drivers/net/ethernet/atheros/ag71xx/ag71xx.h:72:27: note: in expansion of macro 'pr_debug'
#define DBG(fmt, args...) pr_debug(fmt, ## args)
^~~~~~~~
drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c:130:3: note: in expansion of macro 'DBG'
DBG("%s: PHY found at %s, uid=%08x\n",
^~~
scripts/Makefile.build:326: recipe for target 'drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.o' failed
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
remove USB as this is no LED but power control
rename WiFi LED with correct color red (like in stock firmware)
set middle LED to be used for LAN link/activity
Signed-off-by: Andreas Ziegler <dev@andreas-ziegler.de>
The swconfig load operation always triggers 'apply' function which in
this driver currently clears port mirroring flags effectively undoing
port mirroring configuration.
This fix preserves port mirroring flags during apply.
Signed-off-by: Milan Krstic <milan.krstic@gmail.com>
Without this patch PowerCloud CR5000 AR9382 PCIe 5GHz Wifi uses
the mac address from eeprom instead the one specified when
initializing the PCIe chip. There were two issues:
1) ap94_pci_init on the second PCIe wmac is wrong as there is only one
PCIe wmac on this device (the other wmac is the AR1022/AR9342 SoC wmac).
2) Without specifying pdata->use_eeprom there is a failure to load
firmware and caldata.
Thanks to Christian Lamparter (@chunkeey) for the heavy lifting and
help. [0]
[0] <https://github.com/openwrt/openwrt/pull/1613>
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
This add support for TP-Link TL-WA801ND v4 (same as TL-WA801ND v3) :
Specification:
- System-On-Chip: Qualcomm Atheros QCA9533
- CPU/Speed: 650 MHz
- Flash-Chip: Winbond W25Q32BVSIG
- Flash size: 4096 KiB
- RAM: 32 MiB
- Wireless No1: SoC-integrated: QCA9533 2.4GHz 802.11bgn
Flash instructions:
1) To flash the image, rename the file
openwrt-ar71xx-generic-tl-wa801nd-v4-squashfs-factory.bin
to firmware.bin
2) Connect your device to the LAN port, then upload the firmware
through web interface. It will try to download the image and
flash it.
It can take up to 2-3 minutes to finish. When it reaches 100%, the
router will reboot itself.
Signed-off-by: Romain MARIADASSOU <roms2000@free.fr>
RouterBOARD(s) bootloader actully turns Power LED off just before
it starts the kernel. So we need to set the LED default status to On
instead of Keep in order to keep LED on during kernel boot.
This change fixes Power LED off during the kernel boot on the RB91x and
SXT Lite boards.
Fixes: 6cad8ee0bd ("ar71xx: keep the RouterBOARD Power LED in On state")
CC: Mathias Kresin <dev@kresin.me>
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
This adds the build option for UniFi AC Mesh Pro as well as
model detection for it.
The device is a hardware clone of the AC Pro.
- SoC: QCA9563-AL3A (775Mhz)
- RAM: 128MiB
- Flash: 16MiB - dual firmware partitions!
- LAN: 2x 1000M - POE+
- Wireless:
2.4G: QCA9563
5G: UniFi Chip, QCA988X compatible
Signed-off-by: Christoph Krapp <achterin@googlemail.com>
Buttons of AVM FritzBox 4020 are incorrectly flagged as active high.
This was an oversight as RFKill button was working as expected even
with incorrectly flagged GPIO.
Signed-off-by: David Bauer <mail@david-bauer.net>
Netgear WNR612v2 flashed with recent OpenWrt builds suffers from kernel
panic at boot during wireless chip initialization, making device
unusable:
ath: phy0: Ignoring endianness difference in EEPROM magic bytes.
ath: phy0: Enable LNA combining
CPU 0 Unable to handle kernel paging request at virtual address 1000fee1, epc == 801d08f0, ra == 801d0d90
Oops[#1]:
CPU: 0 PID: 469 Comm: kmodloader Not tainted 4.9.120 #0
[ ... register dump etc ... ]
Kernel panic - not syncing: Fatal exception
Rebooting in 1 seconds..
This simple patch fixes above error. It keeps LED table in memory after
kernel init phase for ath9k driver to operate correctly (__initdata
removed).
Also, another bug is fixed - correct array size is provided to function
that adds platform LEDs (this device has only 1 connected to Wifi chip)
preventing code from going outside array bounds.
Fixes: 1f5ea4eae4 ("ar71xx: add correct named default wireless led by using platform leds")
Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
[trimmed commit message]
Signed-off-by: Mathias Kresin <dev@kresin.me>
While "rawnand.h" is available in kernel 4.14,
the default for this target is kernel 4.9 in which "nand.h" should be used.
Add an extra check to include the correct file depending on kernel version
Fixes these build errors:
drivers/mtd/nand/ar934x_nfc.c:16:10: fatal error: linux/mtd/rawnand.h: No such file or directory
#include <linux/mtd/rawnand.h>
^~~~~~~~~~~~~~~~~~~~~
compilation terminated.
Fixes: 318e19ba67 ("ar71xx: add v4.14 support")
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
When checking the outcome of the PHY autonegotiation status, at803x
currently returns false in case the SGMII side is not established.
Due to a hardware-bug, ag71xx needs to fixup the SoCs SGMII side, which
it can't as it is not aware of the link-establishment.
This commit allows to ignore the SGMII side autonegotiation status to
allow ag71xx to do the fixup work.
Signed-off-by: David Bauer <mail@david-bauer.net>
The QCA955X is affected by a hardware bug which causes link-loss of the
SGMII link between SoC and PHY. This happens on change of link-state or
speed.
It is not really known what causes this bug. It definitely occurs when
using a AR8033 Gigabit Ethernet PHY.
Qualcomm solves this Bug in a similar fashion. We need to apply the fix
on a per-device base via platform-data as performing the fixup work will
break connectivity in case the SGMII interface is connected to a Switch.
This bug was first proposed to be fixed by Sven Eckelmann in 2016.
https://patchwork.ozlabs.org/patch/604782/
Based-on-patch-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Signed-off-by: David Bauer <mail@david-bauer.net>
1) Add comments so it's clear why we did things; this may prevent
someone (e.g. me) from sinking time into fixing things that
aren't broken and/or were done for reason.
2) Drop mdio 0 probe/register; we don't use ag1xx mdio bus 0.
3) Cosmetic reording of some code (tested) that makes the defintion
more clear.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
Add missing definitions for the orange WAN LED on the
TL-WR1043N(D) v4 and v5.
Change the name of a MAC address offset constant to
make it consistent with the format of the
existing constants.
Signed-off-by: Tim Thorpe <tim@tfthorpe.net>
TP-Link Archer C59v2 is a dual-band AC1350 router based on
Qualcomm/Atheros QCA9561+QCA9886 chips.
Specification:
- 775/650/258 MHz (CPU/DDR/AHB)
- 128 MB of RAM (DDR2)
- 16 MB of FLASH (SPI NOR)
- 3T3R 2.4 GHz
- 2T2R 5 GHz
- 5x 10/100 Mbps Ethernet
- USB 2.0 port
- UART header on PCB
Flash instruction:
- via web UI:
1. Download openwrt-ar71xx-generic-archer-c59-v2-squashfs-factory.bin
2. Login to router and open the Advanced tab
3. Navigate to System Tools -> Firmware Upgrade
4. Upload firmware using the Manual Upgrade form
- via TFTP:
1. Set PC to fixed ip address 192.168.0.66
2. Download openwrt-ar71xx-generic-archer-c59-v2-squashfs-factory.bin
and rename it to tp_recovery.bin
3. Start a tftp server with the file tp_recovery.bin in its root directory
4. Turn off the router
5. Press and hold Reset button
6. Turn on router with the reset button pressed and wait ~15 seconds
7. Release the reset button and after a short time
the firmware should be transferred from the tftp server
8. Wait ~30 second to complete recovery.
Signed-off-by: Keith Maika <keithm@aoeex.com>
Qxwlan E750G v8 is based on Qualcomm QCA9344.
Specification:
- 560/450/225 MHz (CPU/DDR/AHB)
- 128 MB of RAM (DDR2)
- 8/16 MB of FLASH (SPI NOR)
- 2T2R 2.4G GHz (AR9344)
- 2x 10/100 Mbps Ethernet (PoE support)
- 2x 10/100/1000 Mbps Ethernet
- 7x LED (6 driven by GPIO)
- 1x button (reset)
- 1x DC jack for main power input (9-48 V)
- UART (J23) and LEDs (J2) headers on PCB
Flash instruction (using U-Boot CLI and tftp server):
- Configure PC with static IP 192.168.1.10 and tftp server.
- Rename "sysupgrade" filename to "firmware.bin" and place it in tftp
server directory.
- Connect PC with one of RJ45 ports, power up the board and press
"enter" key to access U-Boot CLI.
- Use the following command to update the device to OpenWrt: "run lfw".
Flash instruction (using U-Boot web-based recovery):
- Configure PC with static IP 192.168.1.xxx(2-254)/24.
- Connect PC with one of RJ45 ports, press the reset button, power up
the board and keep button pressed for around 6-7 seconds, until LEDs
start flashing.
- Open your browser and enter 192.168.1.1, select "sysupgrade" image
and click the upgrade button.
Signed-off-by: 张鹏 <sd20@qxwlan.com>
Qxwlan E750A v4 is based on Qualcomm QCA9344.
Specification:
- 560/450/225 MHz (CPU/DDR/AHB)
- 128 MB of RAM (DDR2)
- 8/16 MB of FLASH (SPI NOR)
- 2T2R 5G GHz (AR9344)
- 2x 10/100 Mbps Ethernet (one port with PoE support)
- 1x miniPCIe slot (USB 2.0 bus only)
- 7x LED (6 driven by GPIO)
- 1x button (reset)
- 1x DC jack for main power input (9-48 V)
- UART (J23) and LEDs (J2) headers on PCB
Flash instruction (using U-Boot CLI and tftp server):
- Configure PC with static IP 192.168.1.10 and tftp server.
- Rename "sysupgrade" filename to "firmware.bin" and place it in tftp
server directory.
- Connect PC with one of RJ45 ports, power up the board and press
"enter" key to access U-Boot CLI.
- Use the following command to update the device to OpenWrt: "run lfw".
Flash instruction (using U-Boot web-based recovery):
- Configure PC with static IP 192.168.1.xxx(2-254)/24.
- Connect PC with one of RJ45 ports, press the reset button, power up
the board and keep button pressed for around 6-7 seconds, until LEDs
start flashing.
- Open your browser and enter 192.168.1.1, select "sysupgrade" image
and click the upgrade button.
Signed-off-by: 张鹏 <sd20@qxwlan.com>
Qxwlan E558 v2 is based on Qualcomm QCA9558 + AR8327.
Specification:
- 720/600/200 MHz (CPU/DDR/AHB)
- 128 MB of RAM (DDR2)
- 8/16 MB of FLASH (SPI NOR)
- 2T2R 2.4 GHz (QCA9558)
- 3x 10/100/1000 Mbps Ethernet (one port with PoE support)
- 4x miniPCIe slot (USB 2.0 bus only)
- 1x microSIM slot
- 5x LED (4 driven by GPIO)
- 1x button (reset)
- 1x 3-pos switch
- 1x DC jack for main power input (9-48 V)
- UART (JP5) and LEDs (J8) headers on PCB
Flash instruction (using U-Boot CLI and tftp server):
- Configure PC with static IP 192.168.1.10 and tftp server.
- Rename "sysupgrade" filename to "firmware.bin" and place it in tftp
server directory.
- Connect PC with one of RJ45 ports, power up the board and press
"enter" key to access U-Boot CLI.
- Use the following command to update the device to OpenWrt: "run lfw".
Flash instruction (using U-Boot web-based recovery):
- Configure PC with static IP 192.168.1.xxx(2-254)/24.
- Connect PC with one of RJ45 ports, press the reset button, power up
the board and keep button pressed for around 6-7 seconds, until LEDs
start flashing.
- Open your browser and enter 192.168.1.1, select "sysupgrade" image
and click the upgrade button.
Signed-off-by: 张鹏 <sd20@qxwlan.com>
The driver is written in such a way that with a board defintion that
connects a fixed phy, mdio, and switch in a certain way, a kernel oops could
result because of lack of previously probed mdio bus.
This commit allows for easier debugging in this case by casting the
correct blame with serial console messages.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
It's a little noisier but makes it obvious when the ar7240 switch was
connected to the MDIO bus, and to which phy device (or the failure
to do so).
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
NB: Error only appears with ag71xx debug messages and dynamic printk
enabled. This is probably why no one has caught it before.
Previously phy probe debug messages used old (now wrong) functions
to get the phy name for printing. There was also the chance of
a NULL pointer in the event no phy_device was found.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The wrong MAC addresses (from the point of view of the physical device
label) were being assigned to the wrong interfaces. Fix that.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The reset button was incorrectly returning KEY_WPS_BUTTON as the key
code. We want KEY_RESTART., so make that fix.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The PCIe wireless MAC address address is better labelled as WMAC
than MAC to emphasize that it is for a wireless interface.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
81d446b045 introduced incomplete
support for this device.
This patch attempts to correct the situation based on OEM source
code.
LED1-3 are GSM mode on OFW (2G/3G/4G) hence unassigned here.
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Tested-by: David Ehrmann <ehrmann@gmail.com>
The active_low flag was missing for the user LED. This LED is open drain
(confirmed in OEM source) and open drain only makes sense for active low
GPIOs.
The two wireless LEDs mentioned in the comments are also #defined for
future reference.
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Tested-by: Ryan Mounce <ryan@mounce.com.au>
e15c63a375 introduced code that was trying
to register GPIO 1 as both an LED and a button. The OEM source makes it
clear that LED1 is not wired to the SoC GPIOs. GPIO 1 is the reset button.
Furthermore the (green) power led default state should also be defined,
(matching OEM source), and it should be used by diag.sh since it's
currently the only software-controllable LED.
This patch fixes these issues and renames the corresponding #defines for
clarity
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
