This fixes some problems with the 6345 support and adds a macro for CPU
identification that is easier on the eyes. The first thing it does is to not
initialize MPI on the 6345 as it does not have PCI. The second thing it does is
to use a static value for the CPU frequency of the 6345 chip to provide an
accurate timer.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
SVN-Revision: 11183
This basically selects the new generic MIPS timer code for BCM963xx and
simplifies the timer setup code.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
SVN-Revision: 11181
The ISR ended up in an endless loop because the TX ISR never got used or masked.
This patch basically makes the TX ISR mask the the TX interrupt when it
encounters it, because it doesn't even use the TX interrupt.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
SVN-Revision: 11179
This patch adds interrupt handling as on AR7. The old code was very messy and
didn't work too well. It also removes the unused file int-handler.S.
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
SVN-Revision: 11178
The load address for BCM963xx is 0x80010000, not 0xf8001000 as in the current
sources. I think this is just a typo, so this patch fixes it (tested on 96345).
Signed-off-by: Axel Gembe <ago@bastart.eu.org>
SVN-Revision: 11177
