This change cherry-picks the following 3 changes from linux-next:
*fb7737 hwspinlock/core: add device tree support
*19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block
*bd5717 hwspinlock: qcom: Correct msb in regmap_field
We're also adding a patch to add the hardware spinlock device nodes on
IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch).
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46655
Linux 4.1 is also affected from the dma issue, so remove the dma
proprties there as well.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 46599
These patches add support for ipq806x NAND flash controller. Most of
these are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/8/3/16
This patch just modifies the kernel code, but doesn't change the config.
It should be harmless.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46568
These are cherry-picked & backported from LKML:
*https://lkml.org/lkml/2015/3/17/19
They are enabled on both 3.18 and 4.1 kernel. Patches 150 to 154 are
applying changes merged since 3.18; they enable mechanisms used by the
ADM driver.
ADM engine is used by the NAND controller, so it is necessary to
bring-up NAND flash support.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46567
Old bootloader (same ones which have DT disabled) don't perform any PCIe
initialization. The consequence is a freeze during PCIe bring-up on
these old u-boot. Same kernel with a newer bootloaders works fine as
they contain the corresponding PCIe init code.
In this change, we'll add the missing init and make sure the kernel
doesn't rely on some preexisting init to get PCIe to work. That includes
the following changes:
*GPIOs: set function & drive strength
*Clocks: add init code for aux & ref clocks
*PCIe driver: additional init of the hardware controller
Tested 3.18 and 4.1 on an AP148 with bootloader branch 0.0.1
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46557
PCIe controller nodes are numbers 0/1/2 in the chipset dtsi file, but
the pinmux nodes are numbers 1/2/3. We'll make it consistent by changing
the pinmux numbering to match the controller's one.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46556
Certain AP148 platforms (and derivative) use bootloaders which did not
have DT enabled.
In order to support these old platforms, we'll now make the following
modifications:
*explicitely add the memory node in the AP148 DT: this used to be added
by new u-boot through a run-time patch mechanism. We'll now add it
explicitely so it works on boots which don't support that feature. New
boots will have the node twice, the second one will be ignored.
*add the zImage generation next to the FIT image for AP148.
Other platforms using non-DT enabled bootloaders may want to leverage
this zImage code to generate their own firmare as well.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 46555
