Global attributes enable_mirror_tx/enable_mirror_rx depend on runtime
value of another global attribute mirror_source_port which just resides
in the memory
The same functionality can be achieved by directly setting port
attribute of the same names. E.g. the following two groups of commands
achieve the same thing
swconfig dev switch0 set mirror_source_port 3
swconfig dev switch0 set enable_mirror_tx 1
swconfig dev switch0 set mirror_source_port 4
swconfig dev switch0 set enable_mirror_tx 1
swconfig dev switch0 port 3 set enable_mirror_tx 1
swconfig dev switch0 port 4 set enable_mirror_tx 1
Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
Looking at the current upstream driver implementation, it seems like the
TX/RX flow control is enabled only if the flow control pause option is
resolved from the device/link partner advertisements (or otherwise set).
On the other hand, our current in-tree driver force enables TX/RX
flow control by default, thus possibly leading to TX timeouts if the
other end sends pause frames (which are not properly handled?):
WARNING: CPU: 3 PID: 0 at net/sched/sch_generic.c:320 dev_watchdog+0x1ac/0x324
NETDEV WATCHDOG: eth0 (mtk_soc_eth): transmit queue 0 timed out
Disabling the flow control on PORT 5 MAC seems to fix this issues as the
pause frames are then filtered out. While at it, I'm removing the if
condition completely as suggested, since this code is run only on mt7621
SoC, so there is no need to check for the silicon revisions.
Ref: https://lists.openwrt.org/pipermail/openwrt-devel/2017-November/009882.html
Ref: https://forum.openwrt.org/t/mtk-soc-eth-watchdog-timeout-after-r11573/50000/12
Suggested-by: Felix Fietkau <nbd@nbd.name>
Reported-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
The device tree property "mediatek,led_polarity" is ignored for
MT7628AN and MT7688. According to the datasheet both SoCs have
the matching register. Therefore the property should be applied
on these two devices as well.
Signed-off-by: Maximilian Pachl <m@ximilian.info>
Reviewed-by: Sungbo Eo <mans0n@gorani.run>
Tested-by: Sungbo Eo <mans0n@gorani.run>
In some boards is requred to change the ephy mdio base address.
This patch add of property "mediatek,ephy-base-address" in gsw
part, which allows to change ephy base address.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
[fixed indentation in header file]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
The port initialisation is based on assumption that phy address and
port number is the same. SoC allow different numbers and some board
have it.
Use phy address instead the port number to make sure that correct
addresses are polled.
In situation when only one PHY with address 0x0 is conected to
port 4, autopolling is broken.
This patch make autopolling correct when port number and phy address
are different.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
The phy handling code forces a phy mdio address and the switch port to
which a phy is attached to be the same. Albeit such a configuration is
used for most boards, it isn't for all.
Pass the switch port number to the ethernet phy connect functions, to
ensure the correct list entry is edited and not the list entry that
matches th phys mdio address.
Use the mdio address with mdiobus_get_phy instead of the port number,
to make sure the expected ethernet phy gets connected.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The whole logic in fe_phy_connect() is based on the asumption that mdio
address and switch port id are equal. Albeit it is true for most
boards, it doesn't is for all.
It isn't yet clear which subtargets/boards require the devicetree less
ethernet phy handling. Hence change the code in a way that it doesn't
touch ethernet phys which were early attached and are already handled.
Signed-off-by: Mathias Kresin <dev@kresin.me>
SoC: MediaTek MT7620a @ 580MHz
RAM: 64M (Winbond W9751G6KB-25)
FLASH: 8MB (Macronix)
WiFi: SoC-integrated: MediaTek MT7620a bgn
WiFi: MediaTek MT7612EN nac
GbE: 1x (RTL8211E)
BTN: WPS - RFKILL/RF 50%/RF 100% toggle
LED: - Wifi 5g (blue)
- Wifi 2g (blue)
- Crossband (green)
- Power (green)
- WPS (green)
- LAN (Green)
UART: UART is present as Pads with throughholes on the PCB. They are
located next to the switch for the wifi configuration
3.3V - RX - GND - TX / 57600-8N1
3.3V is the square pad
Installation
------------
Update the factory image via the web-interfaces (by default:
192.168.9.2/24).
http://192.168.9.2/index.asp
ramips: add Edimax EW-7478AC
SoC: MediaTek MT7620a @ 580MHz
RAM: 64M (Winbond W9751G6KB-25)
FLASH: 8MB (Macronix)
WiFi: SoC-integrated: MediaTek MT7620a bgn
WiFi: MediaTek MT7612EN nac
GbE: 1x (RTL8211E)
BTN: WPS - RFKILL/RF 50%/RF 100% toggle
LED: - Wifi 5g (blue)
- Wifi 2g (blue)
- Crossband (green)
- Power (green)
- WPS (green)
- LAN (Green)
UART: UART is present as Pads with throughholes on the PCB. They are
located next to the switch for the wifi configuration
3.3V - RX - GND - TX / 57600-8N1
3.3V is the square pad
Installation
------------
Update the factory image via the web-interfaces (by default:
http://edimaxext.setup)
Or push wpa button on power on and send firmware via tftp to 192.168.1.6
The EW-7478AC is identical to the EW-7476RPC, except instead of 2 internal
antennas it has 2 external ones.
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
[merge conflict in 01_leds]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
This ioctl is currently routed through generic interface code.
dev_ioctl
dev_ethtool
__ethtool_get_link_ksettings
phy_ethtool_ioctl
Cc: Felix Fietkau <nbd@nbd.name>
Cc: John Crispin <john@phrozen.org>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Some broken ISPs (e.g. Comcast) send DHCPv6 packets with hop limit=0.
This trips up the TTL=0 check in the PPE if enabled.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Current code directly writes the FOE entry to hash_val+1 position
when hash collision occurs. However, it is found that this behavior
will cause the cache and the hardware FOE table to be inconsistent.
For example, there are three flows, and their hashed values are all
equal to 100. The first flow is written to the position of 100. The
second flow is written to the position of 100+1. Then, the logic of
the current code will also write the third flow to 100+1.
At this time, the cache has flow 1 and 2; and the hardware FOE table
has flow 1 and 3, where these two parts store different contents.
So it is necessary to check whether the hash_val+1 is also occupied
before writing. If hash_val+1 is also occupied, we won’t bind th
third flow to the FOE table.
Addition to that, we also cancel the processing of foe_entry removal
because the hardware has auto age-out ability. The hardware will
periodically iterate through the FOE table to find out the time-out
entry and set it as INVALID.
Signed-off-by: HsiuWen Yen <y.hsiuwen@gmail.com>
Sometimes the tuples might be hashed to the same FOE entry.
When this hash collision problem occurs, some of the
connections will not be bound and consequently the CPU
idle rate cannot reach 100%. Therefore, two-way hashing
is adopted to alleviate this problem.
Signed-off-by: HsiuWen Yen <y.hsiuwen@gmail.com>
Some boards have external switches different than mt7530.
This patch allow to use mdio-mode without 0x1f register.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
A buffer is split into multiple descriptors if it exceeds 16 KB.
Apply the same split for the skb head as well (to deal with corner cases
on fraglist support)
Signed-off-by: Felix Fietkau <nbd@nbd.name>
To share mdio addr for IntPHY and ExtPHY,
as described in the documentation (MT7620_ProgrammingGuide.pdf).
(refer: http://download.villagetelco.org/hardware/MT7620/MT7620_ProgrammingGuide.pdf)
when port4 setup to work as gmac mode, dts like:
&gsw {
mediatek,port4 = "gmac";
};
we should set SYSCFG1.GE2_MODE==0x0 (RGMII).
but SYSCFG1.GE2_MODE may have been set to 3(RJ-45) by uboot/default
so we need to re-set it to 0x0
before this changes:
gsw: 4FE + 2GE may not work correctly and MDIO addr 4 cannot be used by ExtPHY
after this changes:
gsw: 4FE + 2GE works and MDIO addr 4 can be used by ExtPHY
Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
When PHY's are defined on the MDIO bus in the DTS, gigabit support was
being masked out for no apparent reason, pegging all such ports to 10/100.
If gigabit support must be disabled for some reason, there should be a
"max-speed" property in the DTS.
Reported-by: James McKenzie <openwrt@madingley.org>
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
Mediatek has a reference platform that pairs an MT7620A with an MT7530W,
where the latter responds on MDIO address 0x1f while both chips respond on
0x0 to 0x4. The driver special-cases this arrangement to make sure it's
talking to the right chip, but two different ways in two different places.
This patch consolidates the detection without the current requirement of
both tests to be separately satisfied in the DTS.
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
The code has some remaining issues that cause ethernet hangs, so
disable it for now until we can get it fixed
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Using the NAPI or netdev frag cache along with other drivers can lead to
32 KiB pages being held for a long time, despite only being used for
very few page fragment.
This can happen if the ethernet driver grabs one or two fragments for rx
ring refill, while other drivers use (and free up) the remaining
fragments. The 32 KiB higher-order page can only be freed once all users
have freed their fragments, which only happens after the rings of all
drivers holding the fragments have wrapped around.
Depending on the traffic patterns, this can waste a lot of memory and
look a lot like a memory leak
Signed-off-by: Felix Fietkau <nbd@nbd.name>
GRO stores packets as fraglist. If they are routed back to the ethernet
device, they need to be re-segmented if the driver does not support
sending fraglists.
Add the missing support for that, along with a missing feature flag that
allows full routed GRO->TSO offload.
Considerably reduces CPU utilization for routing
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Since kernel 4.10 commit 61e84623ace3 ("net: centralize net_device
min/max MTU checking"), the range of mtu is [min_mtu, max_mtu], which
is [68, 1500] by default.
It's necessary to set a max_mtu if a mtu > 1500 is supported.
Signed-off-by: Mathias Kresin <dev@kresin.me>
