The cameo-related recipes can also be used for APRESIA ApresiaLightGS
series devices. So create common definition for the devices manufactured
by Cameo.
And also, the model name of ApresiaLightGS120GT-SS is too long for cameo
header (max: 20 bytes), so use additional variable "CAMEO_BOARD_MODEL"
in Build/cameo-headers instead of DEVICE_MODEL to use the custom name.
(default of CAMEO_BOARD_MODEL: DEVICE_MODEL)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch renames some Cameo specific definitions for image generation.
The same format is also used on APRESIA ApresiaLightGS series devices, not
D-Link specific.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The net_event_work struct is allocated, but only freed in a single case.
Move the allocation to the branch where it is actually needed, and free
it after the work has been done.
Fixes: 03e1d93e07 ("realtek: add driver support for routing offload")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Use generic earlycon on Linux Kernel instead of initialization in platform
setup.
And also, drop bootargs with console= parameter from I-O DATA BSH-G24MB. It
uses 115200bps as baud-rate, the same as default in rtl838x.dtsi.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
On the realtek target, the subtarget makefiles include a KERNEL_PATCHVER
setting, shadowing KERNEL_PATCHVER from target/linux/realtek/Makefile.
This makes the realtek target an exception in this regard, and makes
switching kernel version a bit bothersome. Remove the overrides so all
subtargets use the same kernel version.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Adjust the wrong phy-handle definitions for the sfp ports so that they
match the correct switch ports.
Fixes: 89eb8b50d1 ("realtek: dgs-1210-10mp: add full sfp description")
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
Make the patches apply cleanly again.
Fixes: 4db8598e42 ("realtek: Do not set KERNEL_ENTRY just to avoid NO_EXCEPT_FILL")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use the new timer driver for the RTL930x devices.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[remove old clock provider, select MIPS_EXTERNAL_TIMER and refresh
kernel config]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before calling sched_clock_register(), the timer used to drive the
scheduling clock should already be enabled. Otherwise the kernel log
will show strange time jumps during, and the watchdog might not be
pinged in a timely fashion, resulting in reboots.
[ 0.160281] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 78.104319] clocksource: Switched to clocksource realtek_otto_timer
Fixes: 3cc8011171 ("realtek: resurrect timer driver")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Because this comment is followed by another comment, nothing luckily
breaks, so only a cosmetic change.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
RTL931x kernel builds were patched to bypass the LINKER_LOAD_ADDRESS
parameter, and hardcode it to 0x80220000. This doesn't make much sense,
since value of LINKER_LOAD_ADDRESS, load-ld, only appears to be a copy
of load-y, adjusted to the linker's taste.
Dropping the hacks for bypassing LINKER_LOAD_ADDRESS results in a kernel
that actually starts booting on an RTL9313 (Netgear MS510TXM), but
currently still hangs when the kernel switches timers.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The TP-LINK TL-ST1008F has active-high LEDs, so we need a device tree
property to express this.
Signed-off-by: Lorenz Brun <lorenz@brun.one>
[Tidy up code, restrict changes to 5.15]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
On RTL931x builds, CONFIG_RTL931X was used as a stand-in for
CONFIG_NO_EXCEPT_FILL. Now that the latter is always selected for
devices in the realtek target, this hack can be removed. Resulting
device images are binary identical.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
It seems like we are offsetting the KERNEL_ENTRY to +0x400, which is
also accomplished by the NO_EXCEPT_FILL configuration option.
Since this is the default for MIPS_GENERIC_KERNEL, lets push a little
bit closer to that one by doing the same thing.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
After commit e0d2c59ee995 ("genirq: Always limit the affinity to online
CPUs", 5.10) on Linux, the cpumask passed to irq_set_affinity of irqchip
driver is limited to online CPUs. When irq_do_set_affinity called from
otto timer driver with only one secondary CPU, that CPU is not marked as
online yet, filtered out by cpu_online_mask and fall to error path.
Then, fail to set affinity for that CPU and it leads to instability of
timer on secondary CPU(s).
At least, RTL839x system will be affected.
log:
[ 37.560020] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 37.638025] rcu: 1-...!: (0 ticks this GP) idle=6ac/0/0x0 softirq=0/0 fqs=1 (false positive?)
[ 37.752683] (detected by 0, t=6002 jiffies, g=-1179, q=26293)
[ 37.829510] Sending NMI from CPU 0 to CPUs 1:
[ 37.886857] NMI backtrace for cpu 1 skipped: idling at r4k_wait_irqoff+0x1c/0x24
[ 37.984801] rcu: rcu_sched kthread timer wakeup didn't happen for 5999 jiffies! g-1179 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402
[ 38.132743] rcu: Possible timer handling issue on cpu=1 timer-softirq=0
[ 38.221033] rcu: rcu_sched kthread starved for 6000 jiffies! g-1179 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=1
[ 38.356336] rcu: Unless rcu_sched kthread gets sufficient CPU time, OOM is now expected behavior.
[ 38.474440] rcu: RCU grace-period kthread stack dump:
...
Replace to irq_force_affinity from irq_set_affinity and ignore
cpu_online_mask to fix the issue.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Tested-by: Olliver Schinagl <oliver@schinagl.nl>
While Linus is fine with longer code lines, comments should still be
within the 80 char limit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This is an RTL8393-based switch with 48 RJ-45 and 2 SFP ports.
Hardware
--------
SoC: Realtek RTL8393M
RAM: 128MB DDR3 (Nanya NT5CC64M16GP-DI)
FLASH: 8MB NOR (Macronix MX25L6433F)
ETH: 48x 10/100/1000 Mbps RJ-45 Ethernet
SFP: 2x SFP
BTN:
- 1x Reset button
LEDS:
- 50x Green-Amber leds: lan/sfp status
- 1x Green led: power (Always on)
UART:
- 115200-8-N-1 (CN3, pin-out on PCB)
Everything works correctly except for the 2 SFP ports that are not
working unless you enable it every boot in U-Boot with the command:
rtk network on
Installation
------------
You can install Openwrt using one of the following methods.
Warning: flashing OpenWrt will delete your current configuration.
Warning 2: if the -factory.bix file is not available anymore, you must
follow Method 2.
Method 1:
Check the firmware version currently running on your switch. If you are
running FW V1.0.1.10 or greater, you have to download the firmware
V1.0.1.8 from Netgear website and then flash this version. When the
switch restarts, it should be on version V1.0.1.8. Now you can get the
OpenWrt -factory.bix file and then flash it using the OEM web interface.
Method 2 (requires the UART connection):
Boot the -initramfs-kernel.bin image from U-Boot with these commands:
rtk network on;
tftpboot 0x8f000000 openwrt-realtek-rtl839x-netgear_gs750e-initramfs-kernel.bin;
bootm;
And then flash the -sysupgrade.bin file from OpenWrt.
Revert to stock
---------------
Get the stock firmware from the Netgear website and flash it using the
OpenWrt web interface. Remember to not keep the current configuration
and check the "Force upgrade" checkbox
Once reverted to stock the firmware could complain in the UART console
about mtdblock3 and/or mtdblock4 not being mounted correctly but it
seems to work anyway without any problems. Sample error:
mount: Mounting /dev/mtdblock4 on /mntlog failed: Input/output error
If you want to get rid of these error messages you can boot the
-initramfs-kernel.bin image from U-Boot with these commands:
rtk network on;
tftpboot 0x8f000000 openwrt-realtek-rtl839x-netgear_gs750e-initramfs-kernel.bin;
bootm;
And then erase the corresponding partitions using the command:
For mtdblock3:
mtd erase jffs2_cfg
For mtdblock4:
mtd erase jffs2_log
Now you can reboot the switch and the errors should be gone
Note
----
To get the SFP ports fully working, all the right GPIOs must be found.
In the GPL sources I found these:
- GPIO_14: SFP_TX_DIS1;
- GPIO_19: SFP_TX_DIS0;
Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
Make the patches apply cleanly again.
Fixes: 8dfe69cdfc ("kernel: update nvmem subsystem to the latest upstream")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Added the full SFP description for both SFP ports (lan9, 10) on D-Link
DGS-1210-10MP, which enables hot-plug detection of SFP modules.
Added the patch to both kernel 5.10 and 5.15 dts files.
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
Make the patches apply cleanly again.
Fixes: 8dfe69cdfc ("kernel: update nvmem subsystem to the latest upstream")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is no longer needed now that the kernel is built with a load
address that matches the one hard-coded in the bootloader.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
In target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c,
make rtl838x_pie_rule_write() return non-zero value case of error.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Make sure functions calling rtl838x_smi_wait_op() return its return
value in target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c.
This brings the code style in line with the rtl839x implementation.
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
A behavioural change was introduced with commit 758c88b969 ("realtek:
Whitespace and codestyle cleanup") causing rtl838x_read_phy() and
rtl838x_write_phy() to unconditionally return -ETIMEDOUT. As a result,
probing the device during boot fails:
Error setting up netdev, freeing it again.
rtl838x-eth: probe of 1b00a300.ethernet failed with error -5
Fix the bootloop caused by this regression with kernel 5.15 on rtl838x
devices, by properly returning 0 on success.
Tested on a Netgear GS108T v3, a Netgear GS310TP v1, a Zyxel GS1900-8HP
v1 and an HPE 1920-8G.
Fixes: 758c88b969 ("realtek: Whitespace and codestyle cleanup")
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Upstream generic MIPS uses 0x80100000 and 0x80100400 for the LOADADDR
and ENTRY addresses. As we do not want to diverge from upstream and
patch upstream when not needed, adjust our addresses as well to be
future proof.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
ZyXEL GS1900 devices with SoCs from both the RTL838x and RTL839x
families share the same image structure and size of the firmware
partition. Additionally, the GS1900-48 recipe provided a parameter for
the zyxel-vers command, but this parameter is not used. Deduplicate the
recipes by moving it to target/linux/realtek/image/common.mk.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The listed partition size doesn't match the original partition size, and
actually overlaps with the following partition. The partition node name
for the "firmware" partition also has an extra 'b' compared to the
partition offset.
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900-48 firmware image is identified by the 'AAHN' ID, while the
GS1900-48HP is identified by 'AAHO' [1]. The latter was used, resulting
in the following error message when upgrading via the stock web UI:
Device only can support firmware from V1.00(AAHN.0) and later version
Fix image generation by using the correct ID.
[1] https://download.zyxel.com/GS1900-48/firmware/GS1900-48_2.70(AAHN.3)C0_2.pdf
Link: https://forum.openwrt.org/t/146533
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Suggested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
While cleaning up the makefiles for the realtek target, the order of the
default image generating commands was accidentally changed. This caused
the image signature to end up somewhere in the middle, misaligning the
rootfs. As a result, sysupgrade couldn't verify upgrade images anymore,
and devices end up in a boot loop due to the unaligned (and not found)
rootfs.
Fixes: 94d8b4852b ("realtek: Cleanup Makefiles")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The reset register on RTL93xx not merely have bits to execute
a reset of a hardware component, but also configuration bits for
reset procedures. Keep them during executing a reset.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[backport to 5.10 kernel]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Linus prefers to have loop initializers nice and tightly scoped. In
OpenWRT this has been possible since 41a1a652fb ("kernel: backport
gnu11 upgrade").
This patch cleans up variable scope while trying to do the above for
'simple for loops'.
This cleans up and simplifies some functions and code, and pulls in
variables to a smaller scope.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Our current Makefiles a little bit messy and can be improved somewhat,
both in whitespace and in style.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
The only exception to C++ style comments are SPDX license identifier
markers at the start of C files (even headers have C style markers).
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Fix some ugly whitepsaces and codestyle issues around the realtek sources.
While this is by no means perfect, it catches what it caught.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
A full loop accessing all FDB entries can take several milliseconds
(on RTL839x about 20 ms), so give other kernel tasks a chance to run.
This is especially important for rtl83xx_port_fdb_dump which is itself
called in a loop for all ports by the kernel.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
These two functions are identical apart from writing different values to
the read/write bit. Create a new function rtl_table_exec to reduce code
duplication.
Also replace the unbounded busy-waiting loop. The new implementation may
sleep, but as the hardware typically responds before the first poll, any
callers doing many table accesses still need to make sure not to block
other kernel tasks themselves.
So far, polling timeout errors are only handled by logging an error, but
a return value is added to allow proper handling in the future.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
This function currently prints three messages for every switch port at
KERN_INFO level. This takes a considerable amount of time during bootup
and can even trigger an external watchdog.
Replace these log messages by a single one at KERN_DEBUG level.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
As learning for the CPU port is now disabled globally, the bit in the
TX header doesn't have any effect anymore. Remove it to make the header
consistent with the global configuration.
Originally, this change was intended to be applied before commit
eb456aedfe ("realtek: use assisted learning on CPU port"), which is
why the commit message incorrectly mentions that the TX header already
disables learning.
The reason for disabling learning on the CPU port in the first place is
that it doesn't work correctly when packets are trapped to the CPU and
then forwarded by the CPU to other ports. In that case, the switch would
incorrectly learn the CPU port as source. An example that triggered this
issue are Multicast Listener Reports and IGMP membership reports.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
- rtl83xx_vlan_filtering()
"struct switchdev_trans *trans" parameter was removed[1] and
"struct netlink_ext_ack *extack" was added[2].
[1]: https://www.spinics.net/lists/netdev/msg712250.html
[2]: https://www.spinics.net/lists/netdev/msg722496.html
- rtl83xx_vlan_add/del()
vlan->vid_begin and vlan->vid_end were removed and vlan->vid was
added[3].
[3]: https://www.spinics.net/lists/netdev/msg712248.html
- rtl83xx_vlan_prepare()
"port_vlan_prepare" member was removed from "dsa_switch_ops" struct
in dsa.h[4] and vlan_prepare function should be called from vlan_add
function. Also, change return type of vlan_add function to int.
[4]: https://www.spinics.net/lists/netdev/msg712252.html
- rtl83xx_port_mdb_add()
"port_mdb_prepare" member in "dsa_switch_ops" struct was removed and
preparation need to be done in the function of "port_mdb_add" member
instead. And also, int type need to be returned on "port_mdb_add"
member[5].
[5]: https://www.spinics.net/lists/netdev/msg712251.html
- rtl83xx_port_pre_bridge_flags(), rtl83xx_port_bridge_flags()
The current "port_pre_bridge_flags" member and "port_bridge_flags"
member in "dsa_switch_ops" in dsa.h has flags of
"struct switchdev_brport_flags" type instead[6], so adjust to it.
And, the changed features are passed by flags.mask[7] in
rtl83xx_port_bridge_flags(), so check it before calling function
to enable/disable fieature.
[6]: https://lore.kernel.org/lkml/20210212151600.3357121-7-olteanv@gmail.com/
[7]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e18f4c18ab5b0dd47caaf8377c2e36d66f632a8c
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[shorten final return statement of rtl83xx_port_mdb_add()]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
- 007-5.16-gpio-realtek...: upstreamed on 5.16 and backported to 5.15.3
- 708-brflood-spi.patch : upstreamed
- 709-lag-offloading.patch: upstreamed
- 713-v5.12-net-dsa-... : upstreamed and some implementations are
replaced
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The following drivers were upstreamed and available on 5.15, so drop
from OpenWrt tree.
- realtek-otto-gpio (5.13)
- realtek-rtl-spi (5.12)
- realtek-rtl-intc (5.12)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
add three missing LEDs
- PoE-Max
- Link/Act
- PoE
add two missing buttons
- mode
- reset
The last was dropped in
commit 61a3d0075b ("realtek: update GPIO bindings in the dts files in dts-5.10")
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
General hardware info:
----------------------
D-Link DGS-1210-28MP rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC @ 500MHz,
DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 370W.
Power over Ethernet:
--------------------
The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU.
In order to enable PoE, the realtek-poe package is required. It is
installed by default, but currently it requires the manual editing of
/etc/config/poe. Keep in mind that the port number assignment does not
match on this switch, alway 8 ports are in reversed order: 8-1, 16-9 and
24-17.
LEDs and Buttons:
-----------------
On stock firmware, the mode button is supposed to switch the LED indicators
of all port LEDs between Link Activity and PoE status. The currently
selected mode is visualized using the respective LEDs. PoE Max indicates
that the maximum PoE budget has been reached.
Since there is currently no support for this behavior, these LEDs and
the mode button can be used independently.
Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.
Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
OEM installation from Web Interface:
------------------------------------
1. Make sure you are booting using OEM in image 2 slot. If not, switch to
image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image in vendor firmware via Tools > Backup / Upgrade
Firmware > image1
3. Toogle startup image via System > Firmware Information > Boot from
image1
4. Tools > reboot
Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:
Boot initramfs image from U-Boot:
---------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000
openwrt-rtl838x-generic-d-link_dgs-1210-28mp-f-initramfs-kernel.bin`
command
5. Boot the image with `bootm` command
Signed-off-by: Andreas Böhler <dev@aboehler.at>
should be add/delete or abbreviated add/del
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
The code in dsa.c:rtl83xx_port_enable() was trying to set
vlan_port_tag_sts_ctrl while dealing with differences between SoCs.
However, not only that register has a different address, the register
structure and even the 2-bit value semantic changes for each SoC.
The vlan_port_tag_sts_ctrl field was dropped and converted into a
vlan_port_keep_incoming_tag_set() function that abstracts the different
between SoCs. The macro referencing that register migrated to the SoC
specific c file as it will be privately used by each file.
All magic numbers were converted into macros using BITMASK and
FIELD_PREP.
The vlan_port_tag_sts_ctrl debugfs was dropped for now as it is already
broken for rtl93xx. The best place for SoC specific code might be in each
respective c file and not in if/else clauses.
The final result is:
rtl838x: set ITAG_STS=TAGGED, same as before
rtl839x: set ITAG_STS=TAGGED instead of IGR_P_ITAG_KEEP=0x1, fixing
forwarding of tagged packets
rtl930x: set EGR_ITAG_STS=TAGGED instead of IGR_P_ITAG=0x1, possibly
fixing forwarding of tagged packets
rtl931x: set EGR_ITAG_STS=TAGGED instead of OTPID_KEEP=0x1, possibly
fixing forwarding of tagged packets
Without (EGR_)ITAG_STS=TAGGED, at least for rtl839x, forwarded packets
will drop the vlan tag while packets from the CPU will still have the
correct tag.
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
The rtl930x speed status registers require 4 bits to indicate the speed
status. As such, we want to divide by 8. To make things consistent with
the rest of this code, use a bitshift however.
This bug probably won't affect many users yet, as there aren't many
rtl930x switches in the wild yet with more then 10 ports, and thus a
low-impact bugfix.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[also fix port field extraction]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
After replacing the R4K event timer and clock source with the new
Realtek Otto timer, performance for RTL839x devices was severely
impacted, as reported by Hiroshi.
Research by Markus showed that after commit 4657a5301e ("realtek:
avoid busy waiting for RTL839x PHY read/write"), the ethernet driver
could only update a phy once per timer interval, which also heavily
impacted boot time. On e.g. a Zyxel GS1900-48, this added around a
minute to the time to fully initialise the switch.
By marking the otto clocksource as continuous, the kernel enables it to
be used for high resolution timers. This allows readx_poll_timeout() to
sleep for less than one system timer interval, reducing system dead
time.
Link: https://github.com/openwrt/openwrt/issues/11117
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Cc: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
In rtl83xx_set_features we set bit 3 to enable, and bit 4 to disable
checksuming. Looking at rtl93xx_set_features we however see that for
both enable and disable the same bit is used (bit 4). This can't be
right, especially as bit 4 for rtl83xx seems to be Collision threshold
occupying 2 bits. Change this to make this more logical.
Fixes: 9e8d62e421 ("realtek: enable CRC offloading")
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
L2 learning on the CPU port is currently not consistently configured and
relies on the default configuration of the device. On RTL83xx, it is
disabled for packets transmitted with a TX header, as hardware learning
corrupts the forwarding table otherwise. As a result, unneeded flooding
of traffic for the CPU port can already happen on some devices now. It
is also likely that similar issues exist on RTL93xx, which doesn't have
a field to disable learning in the TX header.
To address this, disable hardware learning for the CPU port globally on
all devices. Instead, enable assisted learning to let DSA write FDB
entries to the switch.
For now, this does not sync local/bridge entries to the switch. However,
support for that was added in Linux 5.14, so the next switch to a newer
kernel version is going to fix this.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Initialize the data structure using memset to avoid the possibility of
writing garbage values to the hardware.
Always set a valid entry type, which should fix writing unicast entries
on RTL930x.
For unicast entries, set the is_static flag to prevent the switch from
aging them out.
Also set the rvid field for unicast entries. This is not strictly
necessary, as the switch fills it in automatically from a non-zero vid.
However, this makes the code consistent with multicast entry setup.
While at it, reorder the statements and fix some style issues (double
space, comma instead of semicolon at end of statement). Also remove the
unneeded priv parameter and debug print for the multicast entry setup
function.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The switches support different actions for incoming ethernet multicast
frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The
current code will set the 2-bit action field to FLOOD (0x3) for most
classes, but the highest bit is always unset for the relevant control
registers. This means the DROP (0x1) action being used for these
classes; whatever class the MSB happens to be in.
For RTL838x, this results in {20,23-2F} frames being dropped, instead of
flooding all ports. On other switch generations, {0F,1F,2F} frames are
dropped. This is inconsistent, and appears to be a mistake. Remove this
inconsistency by flooding all multicast frames with RMA addresses.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The multicast setup function rtl838x_eth_set_multicast_list() checks if
the current SoC is a RTL839x family device. However, the function is
only included in the RTL838x ops table, so this path should never be
taken, making this dead code. rtl839x_eth_set_multicast_list() is
already present in the RTL839x ops table, so it should be safe to remove
this branch.
While touching the code, also re-sort the functions to match sorting
elsewhere, with rtl838x coming before rtl839x.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Currently several messages at KERN_INFO level are printed for every FDB
del/dump operation. This can cause a significant slowdown for example
while using "bridge fdb", and may even trigger a watchdog.
Remove most of these log messages, as the new L2 table debugfs node
should be a good replacement. Change the remaining messages to
KERN_DEBUG level.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Switch to a polling implementation similar to the one for RTL838x, to
allow other kernel tasks to run while waiting.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The new timer is not yet ready for all targets. Avoid interactive
questions during build
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[rename symbol to CONFIG_REALTEK_OTTO_TIMER]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the new timer driver for the RTL839X devices and remove the
no longer needed modules.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the new timer driver for the RTL838X devices. Remove the no
longer needed modules.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Provide some helpful information about the devicetree configuration of
our new driver
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct compatible order in examples]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Now that we provide a clock driver for the Reltek SOCs the CPU frequency might
change on demand. This has direct visible effects during operation
- the CEVT 4K timer is no longer a stable clocksource
- after CPU frequencies changes time calculation works wrong
- sched_clock falls back to kernel default interval (100 Hz)
- timestamps in dmesg have only 2 digits left
[ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ...
[ 0.060000] pid_max: default: 32768 minimum: 301
[ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build
[ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ...
Looking around where we can start the CEVT timer for RTL930X is a good basis.
Initially it was developed as a clocksource driver for the broken timer in that
specific SOC series. Afterwards it was shifted around to the CEVT location,
got SMP enablement and lost its clocksource feature. So we at least have
something to copy from. As the timers on these devices are well understood
the implementation follows this way:
- leave the RTL930X implementation as is
- provide a new driver for RTL83XX devices only
- swap RTL930X driver at a later time
Like the clock driver this patch contains a self contained module that is SOC
independet and already provides full support for the RTL838X, RTL839X and
RTL930X devices. Some of the new (or reestablished) features are:
- simplified initialization routines
- SMP setup with CPU hotplug framework
- derived from LXB clock speed
- supplied clocksource
- dedicated register functions for better readability
- documentation about some caveats
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove unused header includes, remove old CONFIG_MIPS dependency, add
REALTEK_ prefix to driver symbol]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
In *_enable_learning() only address learning should be configured, so
remove enabling forwarding. Forwarding is configured by the respective
*_enable_flood() functions.
Clean up both functions for RTL838x and RTL839x, and fix the comment on
the number of entries.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash RTL838x, RTL839x changes]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Those messages should be printed when entry was found (idx >= 0). Move
them to the right place to not print invalid entry indices.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amden commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The initial state of sds_mode in rtl9300_force_sds_mode() is null and it
will be configured in switch-case. So print message after it.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the generic function of MIPS in Linux Kernel instead of open coding
our own initialisation.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it
will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects
this symbol, so the family check is redudant.
Furthermore, mips_cm_probe() is already called from setup_arch() in
mips/kernel/setup.c before prom_init(), and as such is not required.
Also move mips_cpc_probe() to run just before registering SMP ops.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash SMP change commits, reword commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
This patch only really has an impact on the rtl931x subtarget, which has
no devices. Noboby is currently set up to test these patches either, but
the end result is closer to MIPS_GENERIC, so I do not expect it to cause
issues.
RTL8231 and ethernet phys are not on the same bus, so separate the lock
to each own to cut off the unnecessary dependency.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The workaround for an already-enabled R4K timer used a non-existent
macro CAUSE_DC. Fix compiling by using the actual macro CAUSEF_DC.
Fixes: b7aab19585 ("realtek: SMP handling of R4K timer interrupts")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Until now there has been no good explanation why we mess with the R4K
timer on SMP. After extensive testing and looking at the SDK code it
becomes clear what it is all about.
When we disable the CEVT_R4K module (we will do with the new timer
driver) the R4K timer hardware still fires interrupts on the secondary
CPU. To get around this we have two options:
- Disable IRQ 7
- Stop the counter completely
This patch selects option two because this is the root of evil.. To be
on the safe side we will do it only in case the CEVT_R4K module is
disabled.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The scope of the SMP startup structure is wrong. It is created on the
stack and not as a global variable. This can lead to startup failures.
Fixes: 3f41360eb7 ("realtek: use upstream recommendation for CPU start")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de
OpenWRT's developer guide prefers having actual patches so they an be
sent upstream more easily.
However, in this case, Adding proper fields also allows for `git am` to
properly function. Some of these patches are quite old, and lack much
traceable history.
This commit tries to rectify that, by digging in the history to find
where and how it was first added.
It is by no means perfect and also shows some patches that should have
been long gone.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
When the realtek clock driver was introduced, CONFIG_COMMON_CLK_REALTEK
was not correctly disabled for other subtarget. Add the missing config
flag to fix compilation error on buildbot.
Fixes: 4850bd887c ("realtek: add RTL83XX clock driver")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Don't overwrite AS_DPM and L2LEARNING flags when dest_port is >= 32.
Fixes: 1773264a0c ("realtek: correct egress frame port verification")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Currently we fix interrupts/timers for the secondary CPU by patching
vsmp_init_secondary(). Get a little bit more generic and use the
upstream recommended way instead. Additionally avoid a check around
register_cps_smp_ops() because it does that itself.
See https://lkml.org/lkml/2022/9/12/522
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The interrupt controller depends on two control registers. GIMR enables
or disables interrupts and IRRx routes these to MIPS CPU interrupts 2-7.
Wiki currently states "A value of '0' (in IRRx) disconnects this input from
the output line, independent of the line's setting in GIMR."
Contrary to normal intuition this statement DOES NOT mean, that interrupts
can be disabled by IRRx alone. The sad truth was discovered by enabling
SMP for an Zyxel XGS1010 on the 930x target. It shows that driver and
interrupts behave as follows:
- Timer 0 interrupt 7 has active routing to CPU0 and no routing to CPU1
- Timer 1 interrupt 8 has no routing to CPU0 and active routing to CPU1
- Unmasking (enabling) interrupts writes 1 bits to all GIMR registers
- Masking (disabling) interrupts writes 0 bits to both GIMR registers
During operation we can encounter a situation like
- GIMR bit for a interrupt/CPU combination is set to enabed (=1)
- IRRx routing bits for a interrupt/CPU combination are set to disabed (=0)
This setting already allows the hardware to fire interrupts to the target
CPU/VPE if the other CPU/VPE is currently busy. Especially for CPU bound
timer interrupts this is lethal. If timer interrupt 7 arrives at CPU1 and
vice versa for interrupt 8 the restart trigger gets lost. The timer dies
and a msleep() operation in the kernel will halt endlessly.
Fix this by tracking the IRRx active routing setting in a new bitfield with
0="routing active" and 1="no routing". Enable interrupts in GIMR only
for a interrupt & CPU if routing is active. Thus we have
- GIMR = 0 / IRRx = 0 -> everything disabled
- GIMR = 1 / IRRx > 0 -> active and normal routing
- GIMR = 0 / IRRx > 0 -> masked (disabled) with normal routing
- GIMR = 1 / IRRx = 0 -> no longer possible
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
