This allows specifying PCI devices as children of the PCIe controller
node to pass configuration data to them.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Parameters for dwc2 on lantiq.
A separate dwc2_core_params structure is defined for danube because danube
fifo sizes are large enough to be autodetected. This is not the case on
arx and vrx.
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
Refresh patches for all targets that support kernel 4.4.
Compile-tested on all targets that use kernel 4.4 and aren't marked broken.
Runtime-tested on ar71xx, octeon.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
As specified by e0229a16b0 if the VR9
based router provides FXS ports and they should enabled then the
following must added to the kernel command line:
mem=[TOTALMEMSIZE-2M] vpe1_load_addr=ADDRESS vpe1_mem=2M
By adding mem= parameter a pci device stop working correctly. The
pci-lantiq.c module use get_num_physpages() to compute dynamically the
memory amount of the board.
The mem= make the module to compute in the wrong way the BAR11MASK, so
in this situation the mask is misaligned with the dma area that the
hardware expects.
This patch is a port of what legacy ifxmips_pci.c does.
Signed-off-by: Eddi De Pieri <eddi@depieri.net>
This patch bumps the 4.4 kernel from .28 to .30 and refreshes the patches.
Compile-tested on ar71xx, x86/64, ramips/mt7621, brcm47xx and kirkwood.
Run-tested on ar71xx & ramips/mt7621, brcm47xx and kirkwood (last two confirmed
by P. Wassi).
Signed-off-by: Stijn Segers <francesco.borromini@inventati.org>
(required not-distributable firmware blob - dump it by yourself from original firmware)
Signed-off-by: Eddi De Pieri <eddi@depieri.net>
(cherry picked from commit eb0ce57270d0b5b81b224b9336cf54707497eede)
Modified after cherry-pick:
obj in Makefile
Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
Created minimal patchset based on BB rev 43158 by Eddi De Pieri
14.07/openwrt.git 79472c025449efae9310defad0d3a73cff14d756
If the VR9 based router provides FXS ports and they shoud enabled then
the following must added to the kernel command line:
mem=[TOTALMEMSIZE-2M] vpe1_load_addr=ADDRESS vpe1_mem=2M maxvpes=1
maxtcs=1
To use FXS 2M of RAM are needed for the VPE firmware. The size is set
by vpe1_mem.
The available RAM must be reduced by this size using the mem argument.
A correct load address (example 0x83e00000) for the firmware must be given,
too.
Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
Read the temperature including the decimale place from the CGU_GPHY1_CR
register.
Decrement the temperature read from the register by 38.0 degree celsius.
The temperature range of the sensor is -38.0 to +154 °C and the register
value 0 is equal to -38.0 °C. This fixes the report of unrealistic
temperatures as seen on all tested boards.
Give the SoC a few milliseconds to get the first temperature value. On
some rare occasions there is no temperature value in the register when
read the first time after activation. This leads to a reported
temperature of -38.0 °C on boot.
Only version 1.2 of the vr9 SoC has a temperature sensor. Add a check
to make sure the driver doesn't load on v1.1 vr9 SoCs.
Signed-off-by: Mathias Kresin <dev@kresin.me>
It missed some changes needed for kernel 4.4. This is only used by the
Falcon SoC and not for the xRX SoCs.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Refresh patches for all targets that support kernel 4.4.
compile/run-tested on brcm2708/bcm2710 only.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Backport patches from upstream Linux kernel which are making the
kernel stores the appended dtb not in the same resisters as defined in
the UHI specification, use a separate variable on MIPS.
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
[some modifications]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
With 12fe4b5798 I switched the ath5k
eeprom extraction to an alternate code path. Unfortunately this code
seams to be broken since ages and broke the ath5k EEPROM extraction.
Reported-by: Mohammed Berdai <mohammed.berdai@gmail.com>
Signed-off-by: Mathias Kresin <dev@kresin.me>
Acked-by: John Crispin <john@phrozen.org>
Use priv->wan instead of priv->id as indicator if packets should go to the
Ethernet WAN group (DPID=1) or not (DPID=0). This way, it's independant of
interface names or indexes.
Signed-off-by: Martin Schiller <mschiller@tdt.de>
With an own DMA TX channel for each network device (eth0 + eth1) there
won't be any "tx ring full" errors any more.
This patch also move the spinlocks to the channel level instead of locking
the whole xrx200_hw structure.
Signed-off-by: Martin Schiller <mschiller@tdt.de>
The device tree binding and the associated code duplicates functionality
already patched into the etop driver. The compatible string isn't used
any more. Therefore the whole code can be dropped.
The "mac-increment" property allowed to increment a mac address received
via kernel cmdline. This functionality isn't used by any device and
should be added as etop driver device tree property if required again.
Signed-off-by: Mathias Kresin <dev@kresin.me>
All device tree nodes are using the named properties now and the code
path handling the reg property isn't required any more.
The code related to the ath,eep-flash property has been reformatted to
be better readable.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This patch was introduced in commit r16412 for the brcm47xx target only
and then moved to generic in commit r32395. It was initially added
because of ticket #5186 and should fix some problems with fuse file
systems and MIPS caches. The commit comment in r32395 says that this a
generic problem in MIPS CPUs, but does not name any specifics about
that. There was a fix added to kernel 2.6.21 in commit commit
7575a49f20 "[MIPS] Implement flush_anon_page()." that should fix this
problem, but that was already available before both commits were done
to OpenWrt.
I just tested fuse with ntfs.3g without this patch on a BCM4704
(BMIPS3300 V0.6) SoC and haven't seen any problems. Someone reported
that removing this patch improves some fuse operations by 5 times on
some modern MIPS cores.
My test was only a simple "dd if=/dev/zero of=/mnt/zero bs=5000" to an
USB stick.
This patch removes the patch to OpenWrt, because I assume that it is
not needed any more and Felix, the orginal author, also thinks so.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The lantiq kernel arch code selects CONFIG_RESET_CONTROLLER always, so
it is always selected when the lantiq target is build. we do not need
support for unselected CONFIG_RESET_CONTROLLER option.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
this worked in 3.18 but broke at some point. the old code that loaded a
irq table was incorrewct anyhow as it mapped the irqs int he domain which
should really be done when the driver using them loads them and not the
irq driver itself.
Signed-off-by: John Crispin <john@phrozen.org>
brnboot based devices can have two Image partitions. When flashing
images via the brnboot recovery web interface, the Image partitions are
written alternating.
The current active Image partition is stored in the first byte of the
Primary_Setting partition by using 0x00 for Code_Image_0 and 0x01 for
Code_Image_1.
By using the information about the active "Code Image", it is possible
to ensure that the rootfs belongs to the current booted Image/Kernel.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49281
The VGV7510KW22 has the leds for LAN1-3 connected to pin1 of the phys
and the led for LAN4 connect to pin0 of the phy. This results with the
current configuration in a fast flashing LAN4 led as soon as a network
cable is connected. Something similar was reported on the forum[1] for
the VGV7519 as well.
Since it isn't predicable to which pin a (single) phy led is connected,
use the (default) pin1 functionality
Constant On: 10/100/1000MBit
Blink Fast: None
Blink Slow: None
Pulse: TX/RX
for all ethernet phy leds.
After checking pictures of all vr9 boards, it looks like only the VG3503J
has more than one led connected per phy. Using the phy led device tree
bindings to assign the functionality to the "additional" leds, the
VG3503J phy leds should behave as before.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
[1] https://forum.openwrt.org/viewtopic.php?pid=321523
SVN-Revision: 49270
Instead of using our patch-dtb program just place the device tree
behind the kernel binary and then let the in kernel mechanism fetch it.
This also adds support for having the device tree file in the boot
loader.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 49050
The following patches were dropped because they are already applied
upstream:
- 0038-MIPS-lantiq-fpi-on-ar9.patch
- 0039-MIPS-lantiq-initialize-usb-on-boot.patch
- 0042-USB-DWC2-big-endian-support.patch
- 0043-gpio-stp-xway-fix-phy-mask.patch
All other patches were simply refreshed, except the following:
- 0001-MIPS-lantiq-add-pcie-driver.patch
Changes to arch/mips/lantiq/xway/sysctrl.c (these changes disabled
some PMU gates for the vrx200 / VR9 SoCs) were removed since the
upstream kernel disables unused PMU gates automatically (since
95135bfa7ead1becc2879230f72583dde2b71a0c
"MIPS: Lantiq: Deactivate most of the devices by default").
- 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
Since OpenWrt commit 55ba20afcc drivers
should use of_get_mac_address(). of_get_mac_address_mtd is not
available for drivers anymore since it's called automatically within
of_get_mac_address().
- 0028-NET-lantiq-various-etop-fixes.patch
Same changes as in 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
While refreshing the kernel configuration SPI support had to be moved to
config-4.4 because otherwise M25P80 was disabled.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48307
