There are already ifx_pcie_bios_{map_irq,plat_dev_init} hooks defined in
ifxmips_pcie.c. Instead of defining a new hook we simply re-use the
existing ones (this is basically what the lantiq BSP code does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 45718
The PCIe bus seems to require a hack/workaround when PCI is enabled as
well. Unfortunately this is guarded by an CONFIG_IFX_PCI ifdef, which is
only defined in lantiq's BSP code. The config symbol for the upstream
lantiq PCI driver is CONFIG_PCI_LANTIQ.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 45717
This patch switches calls to readl/writel to their
dwc2_readl/dwc2_writel equivalents which preserve platform endianness.
This patch is necessary to access dwc2 registers correctly on big
endian systems such as the mips based SoCs made by Lantiq. Then dwc2
can be used to replace ifx-hcd driver for Lantiq platforms found e.g.
in OpenWrt.
The patch was autogenerated with the following commands:
$EDITOR core.h
sed -i "s/\<readl\>/dwc2_readl/g" *.c hcd.h hw.h
sed -i "s/\<writel\>/dwc2_writel/g" *.c hcd.h hw.h
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>
SVN-Revision: 44675
Lantiq driver does not work with autodetected fifo sizes so use ones
from original ltq-hcd driver in dwc2. Other values can be
autodetected.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>
SVN-Revision: 44674
Port gpio code from original ltq-hcd driver to dwc2.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>
SVN-Revision: 44673
Add VR9 specific usb initialization bits from ltq-hcd to platform
initialization.
This patch is more of a proof-of-concept than production quality
since the initialization registers are different on other lantiq
platforms.
Signed-off-by: Antti Seppälä <a.seppala@gmail.com>
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>
SVN-Revision: 44672
Some Lantiq SoCs are not able to use buffered writes properly with
Intel command set flash due to the way NOR addresses on EBU are
manipulated. This patch disables buffered writes on those devices.
The only device affected at the moment is ARV4510PW, others use
AMD/Fujitsu command set.
Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
SVN-Revision: 44451
For targets with NO_XIP ltq_mtd->map[i].phys equals -1 and devm_ioremap fails.
Fix this by using pdev->resource[i].start instead.
Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
SVN-Revision: 44450
