Lets give Linux 6.6 a try.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
Refresh kernel config for Linux 6.6.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
Refresh the only remaining downstream patch.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://github.com/openwrt/openwrt/pull/15416
Signed-off-by: Robert Marko <robimarko@gmail.com>
Update default kernel version to 6.6 and drop configs and patches for
kernel 6.1. We can also omit the conditional to include DTS dir.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/15449
Signed-off-by: Robert Marko <robimarko@gmail.com>
Like AVM 1200 these devices also do not use QCA807x PHY at all and thus
they disables all of the individual PHY nodes, however this is not enough
anymore since the conversion to PHY package.
Now its now enough to disable the PHY-s in the package alone, but the PHY
package node itself must also be disabled.
Fixes: 1b931c33a2 ("ipq40xx: adapt to new Upstream QCA807x PHY driver")
Link: https://github.com/openwrt/openwrt/pull/15444
Signed-off-by: Robert Marko <robimarko@gmail.com>
- Soc: MediaTek MT7621AT
- RAM: 512 MB (DDR3)
- Flash: 16 MB (SPI NOR)
- WiFi: MediaTek MT7905DAN, MediaTek MT7975DN
- Ethernet: 1 WAN, 3 LAN (Gigabit)
- Buttons: Reset, Joylink
- LEDs: (red, blue, green), routed to one indicator in the top of the
device
- Power: DC 12V 1A tip positive
- 1 TF Card Slot
The pins for the serial console are already labeled on the board
J4(V, R, T, G). Serial settings: 3.3V, 115200
MAC addresses:
| | MAC | Algorithm |
| ------- | ----------------- | --------- |
| label | dc:d8:xx:xx:xx:01 | label |
| LAN | dc:d8:xx:xx:xx:01 | label |
| WAN | dc:d8:xx:xx:xx:02 | label+1 |
| WLAN 2g | dc:d8:xx:xx:xx:03 | label+2 |
| WLAN 5g | de:d8:xx:xx:xx:04 | label+3 |
1. rename the
openwrt-ramips-mt7621-jdcloud_re-cp-02-squashfs-sysupgrade.bin
to JDCOS.bin
2. start a TFTP server from IP address 192.168.68.10 and serve the
image named JDCOS.bin
3. connect your device to the LAN port
4. power up the router and press any key on the console to interrupt
the boot process.
5. enter the following commands on the router console
1. setenv bootcount 6
2. saveenv
3. reset
> NOTE: wait for the restart, it will automatically fetch the
> image named JDCOS.bin from the TFTP server and write it into
> the flash. After the writing is completed, the router will be
> automatically restarted.
Unable to recognize large-capacity TF card, see #14042. But the patch
https://github.com/openwrt/openwrt/issues/14042#issuecomment-1910769942
works
Co-Authored-By: Jianti Chen <clbcjt@outlook.com>
Signed-off-by: Sheng Huang <shenghuang147@gmail.com>
Hardware:
SoC: MT7981b
RAM: 256 MB
Flash: 128 MB SPI NAND
Ethernet:
1x 2.5Gbps (rtl8221b)
1x 1Gbps (integrated phy)
WiFi: 2x2 MT7981
Buttons: Reset, WPS
LED: 1x multicolor
Solder on UART:
- remove rubber ring on the bottom
- remove screws
- pull up the cylinder, maybe help by push on an ethernet socket with a screwdriver
- remove the (3) screws holding the board in the frame
- remove the board from the frame to get to the screws for the silver, flat heat shield
- remove the (3) screws holding the heat shield
- solder UART pins to the back of the board
- make sure to have the pins point out on side with the black, finned heat spread
- the markings for the pins are going to be below the silver heat shield
- Vcc is not needed
If you don't intend on using the UART outside of the installation process, you might not
want to solder:
- carefully scrape off the thin layer of epoxy on the holes (not the copper)
- place your pin header with the UART attached in the holes
- the pins, starting with the one closest to the socket:
- Vcc (not required)
- GND
- RX
- TX
- either wedge the header or hold it with your fingers so that the pins stay in contact with the board
Installation (UART):
- attach an Ethernet cable to the 1Gbps port (black) on the router
- hold the reset button while powering the router
- press CTRL-C or wait for the timeout to get to the U-Boot prompt
- prepare a TFTP server on the network to supply ..-initramfs-kernel.bin
- use 'tftpboot' in the U-Boot shell to pull the image
- boot the image using 'bootm'
- push the ..-sysupgrade to the router using your preferred method
- perform the upgrade with 'sysupgrade -n'
There is a recovery mechanism that involves fetching a file called 'recovery.bin' but that is not understood yet.
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
FCC ID: A8J-EWS660AP
Engenius ENS1750 is an outdoor wireless access point with
2 gigabit ethernet ports, dual-band wireless,
internal antenna plates, and 802.3at PoE+
Engenius EWS660AP, ENS1750, and ENS1200 are "electrically identical,
different model names are for marketing purpose" according to docs
provided by Engenius to the FCC.
**Specification:**
- QCA9558 SOC 2.4 GHz, 3x3
- QCA9880 WLAN mini PCIe card, 5 GHz, 3x3, 26dBm
- AR8035-A PHY RGMII GbE with PoE+ IN
- AR8033 PHY SGMII GbE with PoE+ OUT
- 40 MHz clock
- 16 MB FLASH MX25L12845EMI-10G
- 2x 64 MB RAM
- UART at J1 populated, RX grounded
- 6 internal antenna plates (5 dbi, omni-directional)
- 5 LEDs, 1 button (power, eth0, eth1, 2G, 5G) (reset)
**MAC addresses:**
Base MAC addressed labeled as "MAC"
Only one Vendor MAC address in flash
eth0 *:d4 MAC art 0x0
eth1 *:d5 --- art 0x0 +1
phy1 *:d6 --- art 0x0 +2
phy0 *:d7 --- art 0x0 +3
**Serial Access:**
the RX line on the board for UART is shorted to ground by resistor R176
therefore it must be removed to use the console
but it is not necessary to remove to view boot log
optionally, R175 can be replaced with a solder bridge short
the resistors R175 and R176 are next to the UART RX pin
**Installation:**
2 ways to flash factory.bin from OEM:
Method 1: Firmware upgrade page:
OEM webpage at 192.168.1.1
username and password "admin"
Navigate to "Firmware Upgrade" page from left pane
Click Browse and select the factory.bin image
Upload and verify checksum
Click Continue to confirm and wait 3 minutes
Method 2: Serial to load Failsafe webpage:
After connecting to serial console and rebooting...
Interrupt uboot with any key pressed rapidly
execute `run failsafe_boot` OR `bootm 0x9fd70000`
wait a minute
connect to ethernet and navigate to
"192.168.1.1/index.htm"
Select the factory.bin image and upload
wait about 3 minutes
**Return to OEM:**
If you have a serial cable, see Serial Failsafe instructions
otherwise, uboot-env can be used to make uboot load the failsafe image
ssh into openwrt and run
`fw_setenv rootfs_checksum 0`
reboot, wait 3 minutes
connect to ethernet and navigate to 192.168.1.1/index.htm
select OEM firmware image from Engenius and click upgrade
**TFTP recovery:**
Requires serial console, reset button does nothing
rename initramfs.bin to '0101A8C0.img'
make available on TFTP server at 192.168.1.101
power board, interrupt boot
execute tftpboot and bootm 0x81000000
**Format of OEM firmware image:**
The OEM software of ENS1750 is a heavily modified version
of Openwrt Kamikaze. One of the many modifications
is to the sysupgrade program. Image verification is performed
simply by the successful ungzip and untar of the supplied file
and name check and header verification of the resulting contents.
To form a factory.bin that is accepted by OEM Openwrt build,
the kernel and rootfs must have specific names...
openwrt-ar71xx-generic-ens1750-uImage-lzma.bin
openwrt-ar71xx-generic-ens1750-root.squashfs
and begin with the respective headers (uImage, squashfs).
Then the files must be tarballed and gzipped.
The resulting binary is actually a tar.gz file in disguise.
This can be verified by using binwalk on the OEM firmware images,
ungzipping then untaring.
Newer EnGenius software requires more checks but their script
includes a way to skip them, otherwise the tar must include
a text file with the version and md5sums in a deprecated format.
The OEM upgrade script is at /etc/fwupgrade.sh.
OKLI kernel loader is required because the OEM software
expects the kernel to be no greater than 1536k
and the factory.bin upgrade procedure would otherwise
overwrite part of the kernel when writing rootfs.
Note on PLL-data cells:
The default PLL register values will not work
because of the external AR8035 switch between
the SOC and the ethernet port.
For QCA955x series, the PLL registers for eth0 and eth1
can be see in the DTSI as 0x28 and 0x48 respectively.
Therefore the PLL registers can be read from uboot
for each link speed after attempting tftpboot
or another network action using that link speed
with `md 0x18050028 1` and `md 0x18050048 1`.
The clock delay required for RGMII can be applied
at the PHY side, using the at803x driver `phy-mode`.
Therefore the PLL registers for GMAC0
do not need the bits for delay on the MAC side.
This is possible due to fixes in at803x driver
since Linux 5.1 and 5.3
Tested-by: Kevin Abraham <kevin@westhousefarm.com>
Signed-off-by: Kevin Abraham <kevin@westhousefarm.com>
Add additional PWM fan cooling step and enable fan on BPi-R4.
Suggested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
We should setup the registers for trapping LLDP packets to the CPU.
Currently, these packets are forwarded to all ports which is not desired
behaviour.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
These registers control the handling of Link Layer Discovery Protocol
(LLDP) packets. This seems to be a typo in the naming.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
This device is similiar to the Wavlink WL-WN531A3.
Hardware
--------
SoC: Mediatek MT7620A
RAM: 64MB
FLASH: 8MB NOR (GigaDevice GD25Q64CS)
ETH:
- 2x 10/100/1000 Mbps Ethernet (RTL8211F)
- 3x 10/100 Mbps Ethernet (integrated in SOC)
WIFI:
- 2.4GHz: 1x (integrated in SOC) (2x2:2)
- 5GHz: 1x MT7612E (2x2:2)
- 4 external antennas
BTN:
- 1x Reset button
- 1x Touchlink button
- 1x Turbo button
- 1x Wps button
- 1x ON/OFF switch
LEDS:
- 1x Red led (system status)
- 1x Blue led (system status)
- 5x Blue leds (ethernet ports)
- 1x Power led
- 1x Wifi led
UART:
- 57600-8-N-1
Everything works correctly.
Installation
------------
Flash the initramfs image in the OEM firmware interface
When Openwrt boots, flash the sysupgrade image otherwise you won't be
able to keep configuration between reboots.
In my case the whole device was locked and there was no way
to flash the image, except for flashing directly to the flash
via an spi-flasher. You need to put the sysupgrade image file at
the beginning of 0x60000.
Notes
-----
1) Router mac addresses:
LAN XX:XX:XX:XX:XX:F0 (factory @ 0x28)
WAN XX:XX:XX:XX:XX:F1 (factory @ 0x2e)
WIFI 2G XX:XX:XX:XX:XX:F2 (factory @ 0x04)
WIFI 5G XX:XX:XX:XX:XX:F3 (factory @ 0x8004)
LABEL XX:XX:XX:XX:XX:F2
Signed-off-by: Eros Brigmann <erosbrigmann@gmail.com>
All kernel config files are refreshed by
`make kernel_oldconfig CONFIG_TARGET={subtarget_target,subtarget}`
"CONFIG_SQUASHFS_DECOMP_SINGLE=y" is manually selected as all ath79
SoCs are single core processors.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
The upcoming 6.6 kernel will introduce a new upstream generic
"gpio-latch" driver. It will conflict with the downstream MikroTik
GPIO latch driver. Let's rename it to avoid any potential issues.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Hardware:
- SoC: MediaTek MT7981B
- CPU: 2x 1.3 GHz Cortex-A53
- Flash: 128 MiB SPI NAND
- RAM: 512 MiB
- WLAN: 2.4 GHz, 5 GHz (MediaTek MT7976CN, 802.11ax)
- Ethernet: 1x 10/100/1000/2500 Mbps RTL8221B WAN, 1x10/100/1000 Mbps MT7981 LAN
- USB 3.0 port
- Buttons: 1 Reset button, 1 slider button
- LEDs: 1x Red, 1x White
- Serial console: internal test points, 115200 8n1
- Power: 5 VDC, 3 A
MAC addresses:
+---------+-------------------+-----------+
| | MAC | Algorithm |
+---------+-------------------+-----------+
| WAN | 80:af:ca:xx:xx:x1 | label+1 |
| LAN | 80:af:ca:xx:xx:x0 | label |
| WLAN 2g | 80:af:ca:xx:xx:x0 | label |
| WLAN 5g | 82:af:ca:xx:xx:x0 | |
+---------+-------------------+-----------+
Installation:
The installation must be done via TFTP by disassembling the router. On other occasions Cudy has distributed intermediate firmware to make installation easier, and so I recommend checking the Wiki for this device if there is a more convenient solution than the one below.
To install using TFTP:
1. Connect to UART.
2. With the router off, press the RESET button. While the router is turning on, the button should continue to be pressed for at least 5 seconds.
3. A u-boot shell will automatically open.
4. Connect to LAN and set your IP to 192.168.1.88/24. Configure a TFTP server and an OpenWrt initramfs-kernel.bin firmware file.
5. Run these steps in u-boot using the name of your file.
setenv bootfile initramfs-kernel.bin
tftpboot
bootm
6. If you can reach LuCI or SSH now, just use the sysupgrade image with the 'Keep settings' option turned off.
Signed-off-by: Luis Mita <luis@luismita.com>
Hardware Specification:
SoC: Mediatek MT7621DAT (MIPS1004Kc 880 MHz, dual core)
RAM: 128 MB
Storage: 128 MB NAND flash
Ethernet: 5x 10/100/1000 Mbps LAN1,LAN2,LAN3,LAN4 & WAN
Wireless: 2.4GHz: Mediatek MT7603EN up to 300Mbps (802.11b/g/n MIMO 2x2)
Wireless: 5GHz: Mediatek MT7615N up to 1733Mbps (802.11n/ac MU-MIMO 4x4)
LEDs: Power (white & amber), Internet (white & amber)
LEDs: 2.4G (White), 5Ghz (White)
Buttons: WPS, Reset
MAC Table
Label xx:xx:xx:xx:xx:EB
LAN xx:xx:xx:xx:xx:EB
2.4Ghz xx:xx:xx:xx:xx:EC
5Ghz xx:xx:xx:xx:xx:ED
WAN xx:xx:xx:xx:xx:EE
Flash instructions:
D-Link normal OEM firmware update page
1. upload OpenWRT factory.bin like any D-Link upgrade image
D-Link Recovery GUI:
1. Push and hold reset button (on the bottom of the device) until power led starts flashing (about 10 secs or so) while plugging in the power cable.
2. Give it ~30 seconds, to boot the recovery mode GUI
3. Connect your client computer to LAN1 of the device
4. Set your client IP address manually to 192.168.0.2 / 255.255.255.0
5. Call the recovery page for the device at http://192.168.0.1/
6. Use the provided emergency web GUI to upload the recovery.bin to the device
Firefox on Windows in a Private Window (incognito) works me
Internet Explorer mode in Microsoft Edge works for others
seems to not work in Linux or virtual machine on Linux for most
some see success using 'curl -v -i -F "firmware=@file.bin" 192.168.0.1'
Thanks to @frkca and @rodneyrod for testing and pushing for its creation
Signed-off-by: Alan Luck <luckyhome2008@gmail.com>
Setting the LED name and abandoning the label and using the
function/color syntax for some TP-Link Archer series routers:
Archer C2 v1, Archer C20 v1, Archer C20i and Archer C50 v1
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Abandoning the label and using the function/color syntax for some dlink
dir series routers: dir-1960-a1, dir-2660-a1, dir-2640-a1, dir-3040-a1
and dir-3060-a1
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Rename from mt7621_dlink_dir-xx60-a1.dtsi to mt7621_dlink_dir_nand_128m.dtsi
and associated group name when creating the mt7621.mk image
Co-authored-by: Alan Luck <luckyhome2008@gmail.com>
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Continuation of commit 8b66f1a. Set the switch address on the MDIO bus to 31.
This is required for all boards currently working with the mt7530 DSA driver.
Fixes: #15419
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Backport patch merged upstream for rgmii-id support in stmmac-ipq806x.
This is needed for some device that directly connets PHY to the gmac
port and require rgmii-id phy-modes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
WPJ419 is still manually defining SPI node, so lets
convert it to use the existing upstream labels for SPI node.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
WPJ419 is still manually defining pinctrl node, so lets
convert it to use the existing upstream labels for pinctrl node.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
WPJ419 is still manually defining PCIe node, so lets
convert it to use the existing upstream labels for PCIe node and while we
are here use the -gpios suffix instead.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some boards are still defining MDIO nodes under soc instead of using the
existing upstream labels to reference them so convert them.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some boards are still defininig I2C nodes under soc instead of using the
existing upstream labels to reference them so convert them.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some boards are still defininig UART nodes under soc instead of using the
existing upstream labels to reference them so convert them.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
This device does not have NAND enabled at all and NAND is the only consumer
of QPIC BAM DMA, so drop the node.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
WPJ419 is still manually defining dma nodes(And even some labels), so lets
convert it to use the existing upstream labels for DMA nodes.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently, a lot of boards are still not using the existing label to
reference the crypto node, so lets rectify this.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently, a lot of boards are still not using the existing label to
reference the prng node, so lets rectify this.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently, a lot of boards are still not using the existing label to
reference the watchdog node, so lets rectify this.
Link: https://github.com/openwrt/openwrt/pull/15415
Signed-off-by: Robert Marko <robimarko@gmail.com>
The way to register the switch MDIO bus and PHYs on the bus in upstream
Linux is more strict and requires each PHY to explicitely state the
interrupt instead of assuming it in case the 'interrupts' property in DT
is missing.
Add missing interrupts for the PHYs of the build-in 4x1GE switch of the
MT7988 SoC.
Fixes: 4354b34f6f ("generic: 6.6: sync mt7530 DSA driver with upstream")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
To fix issue #15304
Correct br-lan ports 1-4 so that phy-handle matches reg nr not port label.
Fixes: eb13076e77 ("mediatek: fix DTS defining mt7530 switch phys but not referencing them")
Signed-off-by: Magnus Lindström <magnus1089@hotmail.com>
