Instead of letting each target define it themselves, create on in
include/image.mk and let the targets use it.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 46596
One argument was removed with kernel 4.1 from xhci_handshake() which
caused a compile error.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46369
Follow upstream patch and handle it using &uart0. Also disable &uart1 as
it's most likely unused. This will allow us to get valuable reports and
upstream these changes.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 46140
This patch adds the missing parts to use the upstream Broadcom PCIe
driver and makes use of it.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46130
Instead of setting the l2c_aux_val variable in the board code make it
possible to set these through device tree and make use of that.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46129
This only removes the patches already applied upstream and makes the
rest apply cleanly.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46128
This stabilizes USB support. The old patch was handling initialization
in a different order that was causing some problems with few USB 3.0
devices. Some weren't detected, some were working unstable, sometimes
USB 3.0 could hang the whole controller.
A still known issue (but not a regression) is controller hang triggered
by connecting USB 1.1 device when not having OHCI controller enabled
(kmod-usb-ohci).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45997
Extracting TRX to separated file in /tmp/ just wastes some RAM while we
can just pass a proper extracting command to the default_do_upgrade.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45912
Extracting full TRX out of vendor format is not needed as otrx supports
passing TRX offset. This saves some RAM during sysupgrade.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45911
There is also a OHCI controller, activate it for USB 1.1 support.
This should close#19601.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 45716
This device seems to have switch port 7 connected to the CPU:
vlan1ports=1 2 3 5 7*
vlan2ports=0 7u
it should be handled by eth1 and NVRAM seems to confirm that (no
et0macaddr entry, existing et1macaddr & et1phyaddr entries).
One of the remaining ports (4/8?) may be connected to the Quantenna SoC.
Original firmware boot log contains following messages:
(0x00,0x5d)Port 5 States Override: 0xfb
(0x00,0x5f)Port 7 States Override: 0xfb
(0x00,0x0e)Port 8 States Override: 0x0a
(why does it force port 5 state?!)
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45692
It has 3 Ethernet interfaces, each of them connected to separated switch
port. Default NVRAM uses switch port 8 as CPU which is connected to the
3rd interface (eth2).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45681
