The Pine64(+) and the SoPine64 baseboard has two USB ports. One of
these (the lower) is connected directly to a USB host, the other
one's (upper) PHY is shared with the separate OTG controller. In
order to get it working, MUSB support needs to be enabled.
As there are other targets which compile MUSB support into the kernel
and not package it into modules, the same is done here.
[ 1.348760] usb usb5: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.04
[ 1.357029] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 1.364250] usb usb5: Product: MUSB HDRC host driver
[ 1.369219] usb usb5: Manufacturer: Linux 5.4.99 musb-hcd
[ 1.374617] usb usb5: SerialNumber: musb-hdrc.1.auto
[ 1.379891] hub 5-0:1.0: USB hub found
[ 1.383677] hub 5-0:1.0: 1 port detected
[...]
[ 697.299440] usb 1-1: new high-speed USB device number 2 using ehci-platform
[ 697.461855] usb 1-1: New USB device found, idVendor=090c, idProduct=1000, bcdDevice=11.00
[ 697.470038] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 697.477180] usb 1-1: Product: USB Flash Disk
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
1. Use upstream accepted NVMEM patches
2. Minor fix for BCM4908 partitioning
3. Support for Linksys firmware partitions on Northstar
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
The original GL.iNet firmware has two different mac addresses in the
factory/art partition. The first one is for the WAN interface only and the
second one is for both lan0 and lan1.
But the original submission for OpenWrt didn't initialize the mac
addresses of the LAN ports for the DSA device at all. The ethernet mac
address was then used for all DSA ports.
Fixes: 050c24f05c ("mvebu: add support for GL.iNet GL-MV1000")
Signed-off-by: Sven Eckelmann <sven@narfation.org>
There are only two lan ports and one wan port on Youku yk1
Fixes: e9baf8265b ("ramips: add support for Youku YK1")
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
[add Fixes:]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
On NEC Aterm WG1200CR, the MAC address for WAN is printed in the label
on the case, not LAN.
This patch fixes this issue.
Fixes: 50fdc0374b ("ath79: provide label MAC address")
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The original patch to support this device advertised support for the reset
button and the "switch" in the commit message. But neither were actually
integrated in the device tree or documented anywere.
The button itself is now used to trigger a reset (as described in the
official GL.iNet documentation). The switch itself is registered as BTN_0
like other devices from GL.iNet in ath79.
Fixes: 050c24f05c ("mvebu: add support for GL.iNet GL-MV1000")
Signed-off-by: Sven Eckelmann <sven@narfation.org>
The CONFIG_USERIO option is unset in multiple target configurations. On
the sunxi target it is activated. Move the kernel configuration option
to the generic kernel configuration.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Instead of deactivating this in every target config, deactivate it once
in the generic kernel config. I was asked for this config option in a
x86 64 build in OpenWrt 21.02.
Fixes: 87046e87e2 ("kernel: add missing kernel config symbol")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Bump to 5.10.26 reversed dependencies on IOMMU for CONFIG_VFIO thus
malta (at least) prompted for this new symbol.
Set it to 'false' in the default config. rockchip & X86 enable it in
target specific configs.
Thanks to Tony Ambardar for falling over this one
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
This adds detection of the Sophos SG-105 and Sophos XG-105 models
and assignment of ethernet ports these models have to LAN/WAN.
Signed-off-by: Stan Grishin <stangri@melmac.net>
It's helpful for accessing booting data (DTS, kernel, etc.). It has to
be used carefully as CFE's JFFS2 support is quite dumb. It doesn't
recognize deleted files and has problems handling 0 inode.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Populate the recovery and production partitions of the generated sdcard
image for the Bananapi BPi-R64.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
After backporting upstream ehci overcurrent patches we need to use spurious-oc
instead of ignore-oc.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
This patch really annoys me, either it needs to go upstream or be
dropped, so it's going to be dropped here.
Checking drivers/platform/x86/pcengines-apuv2.c it also appears to be
incomplete since it mentions different dmi board names depending on bios
version.
/* APU2 w/ legacy BIOS < 4.0.8 */ is 'APU2'
/* APU2 w/ legacy BIOS >= 4.0.8 */ is 'apu2'
/* APU2 w/ mainline BIOS */ is 'PC Engines apu2'
So the patch, if applicable at all, only 'works' for legacy BIOS >=
4.0.8
My APU2 on mainline BIOS reboots fine without this patch. So let's see
if anyone screams and when they do question why legacy bios. If patch
DOES need to be re-introduced then it needs to go upstream first.
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
Straightforward refresh of patches using update_kernel.
Removed (reverse-applicable):
bmips/patches-5.10/010-v5.11-net-dsa-implement-a-central-TX-reallocation-procedur.patch
Run tested: x86_64 (apu2)
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
Straightforward refresh of patches using update_kernel.
Run tested: x86_64 (apu2)
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
These PCI drivers are a bit hacky and definitely not suitable for upstreaming,
but hopefully we can use them as a base for developing proper upstream PCI
drivers.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Otherwise, the last defined value will be set for all devices.
Fixes: c6c8d597e1 ("realtek: Add generic zyxel_gs1900 image definition")
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Youku YK-L1 has a huge storage space up to 32 MB. It is better to
use a higher spi clock to read or write serial nor flash chips.
Youku YK-L1 has Winbond w25q256fvfg on board that can support
104 MHz spi clock so 48 MHz is safe enough.
The real frequency can only be sysclk(580MHz ) /3 /(2^n) so 80 MHz
defined in dts file will set only 48 MHz in spi bus.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Add the same patch to 5.10 too. The patch is in process of being
upstreamed.
Fixes: 8cc0fa8fac ("ath79: cfi: cmdset_0002: amd chip
0x2201 - write words")
Signed-off-by: Mauri Sandberg <sandberg@mailfence.com>
[add Fixes:]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This device is a wireless router working on 2.4GHz band based on
Qualcom/Atheros AR9132 rev 2 SoC and is accompanied by Atheros AR9103
wireless chip and Realtek RTL8366RB/S switches. Due to two different
switches being used also two different devices are provided.
Specification:
- 400 MHz CPU
- 64 MB of RAM
- 32 MB of FLASH (NOR)
- 3x3:2 2.4 GHz 802.11bgn
- 5x 10/100/1000 Mbps Ethernet
- 4x LED, 3x button, On/Off slider, Auto/On/Off slider
- 1x USB 2.0
- bare UART header place on PCB
Flash instruction:
- NOTE: Pay attention to the switch variant and choose the image to
flash accordingly. (dmesg / kernel logs can tell it)
- Methods for flashing
- Apply factory image in OEM firmware web-gui.
- Sysupgrade on top of existing OpenWRT image
- U-Boot TFPT recovery for both stock or OpenWRT images:
The device U-boot contains a TFTP server that by default has
an address 192.168.11.1 (MAC 02:AA:BB:CC:DD:1A). During the boot
there is a time window, during which the device allows an image to
be uploaded from a client with address 192.168.11.2. The image will
be written on flash automatically.
1) Have a computer with static IP address 192.168.11.2 and the
router device switched off.
2) Connect the LAN port next to the WAN port in the device and the
computer using a network switch.
3) Assign IP 192.168.11.1 the MAC address 02:AA:BB:CC:DD:1A
arp -s 192.168.11.1 02:AA:BB:CC:DD:1A
4) Initiate an upload using TFTP image variant
curl -T <imagename> tftp://192.168.11.1
5) Switch on the device. The image will be uploaded subsequently.
You can keep an eye on the diag light on the device, it should
keep on blinking for a while indicating the writing of the image.
General notes:
- In the stock firmware the MAC address is the same among all
interfaces so it is left here that way too.
Recovery:
- TFTP method
- U-boot serial console
Differences to ar71xx platform
- This device is split in two different targets now due to hardware
being a bit different under the hood. Dynamic solution within the same
image is left for later time.
- GPIOs for a sliding On/Off switch, marked 'Movie engine' on the device
cover, were the wrong way around and were renamed qos_on -> movie_off,
qos_off -> movie_on. Associated key codes remained the same they were.
The device tree source code is mostly based on musashino's work
Signed-off-by: Mauri Sandberg <sandberg@mailfence.com>
Generally, in upstream CFI flash memory driver uses buffers for write
operations. That does not work with AMD chip with id 0x2201 and we must
resort to writing word sized chunks only. That is, to not apply general
buffer write functionality for this given chip.
Without the patch kernel logs will be flooded with entries like below:
MTD do_erase_oneblock(): ERASE 0x01fa0000
MTD do_write_buffer(): WRITE 0x01fa0000(0x00001985)
MTD do_erase_oneblock(): ERASE 0x01f80000
MTD do_write_buffer(): WRITE 0x01f80000(0x00001985)
MTD do_write_buffer_wait(): software timeout, address:0x01f8000a.
jffs2: Write clean marker to block at 0x01a60000 failed: -5
MTD do_erase_oneblock(): ERASE 0x01f60000
MTD do_write_buffer(): WRITE 0x01f60000(0x00001985)
MTD do_write_buffer_wait(): software timeout, address:0x01f6000a.
jffs2: Write clean marker to block at 0x01a40000 failed: -5
References: http://patchwork.ozlabs.org/project/linux-mtd/patch/20210309174859.362060-1-sandberg@mailfence.com/
Signed-off-by: Mauri Sandberg <sandberg@mailfence.com>
[added link to usptream fix submission]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Physical port order watched from the back of the device is:
4 / 3 / 2 / 1 / WAN which also matches corresponding leds.
This patch corrects LuCI switch webpage LAN port order.
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
[improve commit title, fix sorting in 02_network]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Ran update_kernel.sh in a fresh clone without any existing toolchains.
Manually rebased:
bcm27xx/950-0993-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
layerscape/701-net-0231-enetc-Use-DT-protocol-information-to-set-up-the-port.patch
Build system: x86_64
Build-tested: ipq806x/R7800
Run-tested: ipq806x/R7800
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[remove accidental whitespace edit]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Improve compatibility of the device tree include file. Now a new .dtsi
file will support both PSG1218A, PSG1218B and K2G.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
[improve commit title, rebase]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
From many teardown image in the internet, I find Phicomm K1/k2 series use
Winbond W25Q64/W25Q128 or GigaDevice GD25Q64/GD25Q128 Flash chips. both of
them support 100+ MHz clock spi operate and fast-read instruction. PSG1218
with W25x or GD25x has been tested and it can run well in OpenWrt v19.07.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
[improve commit title]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
HIWIFI HC5x61 devices support high speed spi clock up to 100+ MHz.
So set spi frequency to 80 MHz here (Due to frequency division the
real clock is 48 MHz).
I have tested HC5661 and it can run well in OpenWrt v19.07.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
[adjust commit title and wrap message]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
There is an ASMedia ASM1480 PCIe switch found on mt7622-rfb1 and the
BPi-R64, allowing the user to switch between SATA and PCIe1 which share
the same pins on the SoC.
This chip is not present on the Linksys E8450, it doesn't have SATA.
Remove definitions for GPIO90 from DTSI to prevent it from being
copy&pasted or otherwise causing confusion.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
