filogic: Add support for D-Link AQUILA PRO AI M30
Specification:
- MT7981 CPU using 2.4GHz and 5GHz WiFi (both AX)
- 1GB RAM
- 16MB NOR
- 128MB NAND
- 3 LEDs (red, green, blue, white)
- 2 buttons (reset, user defined)
- 1 2.5Gbit WAN port (Airoha EN8811h)
- 1 1Gbit LAN ports
- 1 single lane M.2 SSD slot
- 1 mikroBus socket
- externel HW WDT (25s refresh time)
- i2c RTC (with battery backup)
Serial Interface
- UBS-C CDC-ACM
- 3 Pins GND, RX, TX
- Settings: 115200, 8N1
MAC addresses are not populated on the early samples.
Signed-off-by: John Crispin <john@phrozen.org>
Add ubi volumes for mt7988a-rfb and support for using factory data
for Ethernet MAC addresses and MT7996 WLAN calibration data.
Also add rootdisk handle. Removes the need to keep using nmbm
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Hardware:
SoC: MT7981b
RAM: 256 MB
Flash: 128 MB SPI NAND
Ethernet:
1x 2.5Gbps (rtl8221b)
1x 1Gbps (integrated phy)
WiFi: 2x2 MT7981
Buttons: Reset, WPS
LED: 1x multicolor
Solder on UART:
- remove rubber ring on the bottom
- remove screws
- pull up the cylinder, maybe help by push on an ethernet socket with a screwdriver
- remove the (3) screws holding the board in the frame
- remove the board from the frame to get to the screws for the silver, flat heat shield
- remove the (3) screws holding the heat shield
- solder UART pins to the back of the board
- make sure to have the pins point out on side with the black, finned heat spread
- the markings for the pins are going to be below the silver heat shield
- Vcc is not needed
If you don't intend on using the UART outside of the installation process, you might not
want to solder:
- carefully scrape off the thin layer of epoxy on the holes (not the copper)
- place your pin header with the UART attached in the holes
- the pins, starting with the one closest to the socket:
- Vcc (not required)
- GND
- RX
- TX
- either wedge the header or hold it with your fingers so that the pins stay in contact with the board
Installation (UART):
- attach an Ethernet cable to the 1Gbps port (black) on the router
- hold the reset button while powering the router
- press CTRL-C or wait for the timeout to get to the U-Boot prompt
- prepare a TFTP server on the network to supply ..-initramfs-kernel.bin
- use 'tftpboot' in the U-Boot shell to pull the image
- boot the image using 'bootm'
- push the ..-sysupgrade to the router using your preferred method
- perform the upgrade with 'sysupgrade -n'
There is a recovery mechanism that involves fetching a file called 'recovery.bin' but that is not understood yet.
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu>
Add additional PWM fan cooling step and enable fan on BPi-R4.
Suggested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Hardware:
- SoC: MediaTek MT7981B
- CPU: 2x 1.3 GHz Cortex-A53
- Flash: 128 MiB SPI NAND
- RAM: 512 MiB
- WLAN: 2.4 GHz, 5 GHz (MediaTek MT7976CN, 802.11ax)
- Ethernet: 1x 10/100/1000/2500 Mbps RTL8221B WAN, 1x10/100/1000 Mbps MT7981 LAN
- USB 3.0 port
- Buttons: 1 Reset button, 1 slider button
- LEDs: 1x Red, 1x White
- Serial console: internal test points, 115200 8n1
- Power: 5 VDC, 3 A
MAC addresses:
+---------+-------------------+-----------+
| | MAC | Algorithm |
+---------+-------------------+-----------+
| WAN | 80:af:ca:xx:xx:x1 | label+1 |
| LAN | 80:af:ca:xx:xx:x0 | label |
| WLAN 2g | 80:af:ca:xx:xx:x0 | label |
| WLAN 5g | 82:af:ca:xx:xx:x0 | |
+---------+-------------------+-----------+
Installation:
The installation must be done via TFTP by disassembling the router. On other occasions Cudy has distributed intermediate firmware to make installation easier, and so I recommend checking the Wiki for this device if there is a more convenient solution than the one below.
To install using TFTP:
1. Connect to UART.
2. With the router off, press the RESET button. While the router is turning on, the button should continue to be pressed for at least 5 seconds.
3. A u-boot shell will automatically open.
4. Connect to LAN and set your IP to 192.168.1.88/24. Configure a TFTP server and an OpenWrt initramfs-kernel.bin firmware file.
5. Run these steps in u-boot using the name of your file.
setenv bootfile initramfs-kernel.bin
tftpboot
bootm
6. If you can reach LuCI or SSH now, just use the sysupgrade image with the 'Keep settings' option turned off.
Signed-off-by: Luis Mita <luis@luismita.com>
Continuation of commit 8b66f1a. Set the switch address on the MDIO bus to 31.
This is required for all boards currently working with the mt7530 DSA driver.
Fixes: #15419
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
The way to register the switch MDIO bus and PHYs on the bus in upstream
Linux is more strict and requires each PHY to explicitely state the
interrupt instead of assuming it in case the 'interrupts' property in DT
is missing.
Add missing interrupts for the PHYs of the build-in 4x1GE switch of the
MT7988 SoC.
Fixes: 4354b34f6f ("generic: 6.6: sync mt7530 DSA driver with upstream")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
To fix issue #15304
Correct br-lan ports 1-4 so that phy-handle matches reg nr not port label.
Fixes: eb13076e77 ("mediatek: fix DTS defining mt7530 switch phys but not referencing them")
Signed-off-by: Magnus Lindström <magnus1089@hotmail.com>
There was a typo in commit 5709254690 ("mediatek: bpi-r4: store random
MAC addresses for the BPi-R4"). Let's fix it and also add support for
the bpi-r4-poe variant.
Fixes: 5709254690 ("mediatek: bpi-r4: store random MAC addresses for the BPi-R4")
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
In commit cd4de3251c ("mediatek: wait for fitblk rootfs"), the linux
6.6 files and patches has been forgotton to be fixed.
Fixes: cd4de3251c ("mediatek: wait for fitblk rootfs")
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
In commit cd4de3251c ("mediatek: wait for fitblk rootfs"), the linux
6.6 files and patches has been forgotton to be fixed.
Fixes: cd4de3251c ("mediatek: wait for fitblk rootfs")
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Adding the aliases also for Linux 6.6 was forgotten and is required for
U-Boot to hand down persistent MAC addresses to Linux.
Fixes: 5709254690 ("mediatek: bpi-r4: store random MAC addresses for the BPi-R4")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The patch "710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch"
makes use of "syscon_regmap_lookup_by_phandle" which requires that
"syscon" be in the compatible list.
Without this patch, PCIe probe will fail with the following error:
[ 1.287467] mtk-pcie 1a143000.pcie: host bridge /pcie@1a143000 ranges:
[ 1.294019] mtk-pcie 1a143000.pcie: Parsing ranges property...
[ 1.299901] mtk-pcie 1a143000.pcie: MEM 0x0020000000..0x0027ffffff -> 0x0020000000
[ 1.307954] mtk-pcie 1a143000.pcie: missing hifsys node
[ 1.313185] mtk-pcie: probe of 1a143000.pcie failed with error -22
Fixes: 4c6e9a9943 ("kernel: bump 6.6 to 6.6.30")
Signed-off-by: Rany Hany <rany_hany@riseup.net>
This adds support for the bpi-r4 variant with internal 2.5G PHY and
additional ethernet port instead of second sfp.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Move the common parts of the mt7988a-bananapi-bpi-r4.dts to a dtsi file.
This is done to prepare support for the 2.5G Ethernet Variant.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This reverts commit 3fe239fcf8.
Now that we switched to Linux 6.6 this is no longer needed, and resulted
in a left-over file because it's removal was not included in the commit
removing all the other files intended for Linux 6.1.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Remove unnecessary 'if' macros for previous kernel versions.
After removing kernel 6.1 the kernel is always >= 6.6 so the conditions
are unnecessary.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Despite coming with multiple I2C EEPROMs supposedly dedicated for that
purpose, the BPi-R4 does not seem to have factory assigned MAC addresses.
Hence, just like for all other BPi boards, store a randomly generated
MAC address on first boot and derive WAN and Wi-Fi MAC addresses from
that as well. Not perfect, but better than random on every boot.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The compatible string for the MediaTek MT7988 SoC ended up being
'mediatek,mt7988a' instead of 'mediatek,mt7988' in the now upstream
dtsi. Adapt the cpufreq driver so support for frequency scaling is
again usable.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
For all boards currently working with the mt7530 DSA driver we can
be sure that the address of the switch on the MDIO bus is 31 --
simply because that address is hard-coded in the driver and the
address from the Device Tree is being ignore.
An upcoming patch will add support for MT753x ICs which are programmed
to addresses different from 0x1f using bootstrap pins. As a result the
address from the Device Tree will then be taken into account, which
will break currently working boards which got the address set to
anything else than 31.
While at it also unify the syntax in Device Tree to always us a decimal
value for the 'reg' property.
* mt7622-buffalo-wsr-3200ax4s.dts
Cosmetic change 'reg = <0x1f>' -> 'reg = <31>'
* mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi
Wrong address: 0 -> 31
* mt7622-elecom-wrc-x3200gst3.dts
Wrong address: 0 -> 31
* mt7622-linksys-e8450.dtsi
Wrong address: 0 -> 31
* mt7622-ruijie-rg-ew3200.dtsi
Wrong address: 0 -> 31
* mt7622-xiaomi-redmi-router-ax6s.dts
Wrong address: 0 -> 31
* mt7629-iptime-a6004mx.dts
Wrong address: 2 -> 31
* mt7981b-zbtlink-zbt-z8102ax.dts
Cosmetic change 'reg = <0x1f>' -> 'reg = <31>'
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use 'mediatek,mt7988a' instead of 'mediatek,mt7988' as compatible
string to be in-sync with upstream and no longer break the cpufreq
driver which was also kept in sync with upstream.
Fixes: 56dd6b473b ("mediatek: sync cpufreq support with changed compatible string")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Backport patches for support of generic spi-nor from SFDP data for
kernel 6.1.
Kernel 5.15 have major rework of the info flags and it's not trustable
to backport this amount of changes and expect correct function of it.
All affected patches automatically refreshed using make
target/linux/refresh.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The upstream solution to define the MDIO bus in DT is a bit
more strict than our previous downstream solution doing the same thing
and now requires switch PHYs to be referenced in DT as well.
Arınç Ünal told us in #15141:
"With [the now upstream patch written by him which we backported], the
switch MDIO bus won't be assigned to ds->user_mii_bus when the switch
MDIO bus is defined on the device tree anymore. This was not the case
with the downstream patch.
When ds->user_mii_bus is populated, DSA will 1:1 map the port with
PHY. Meaning port with address 1 will be mapped to PHY with address 1.
Because that ds->user_mii_bus is not populated when the switch MDIO
bus is defined on the device tree, on every port node, the PHY address
must be supplied by the phy-handle property."
Add those phy-handles to affected devices' DT.
Fixes: 4354b34f6f ("generic: 6.6: sync mt7530 DSA driver with upstream")
Fixes: 401a6ccfaf ("generic: 6.1: sync mt7530 DSA driver with upstream")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Fix also some Chinese GB18030 -> UTF-8 encoding problems
(translated the Chinese strings to English):
修改 -> modification
port8~port10的设置在另外一个register ->
port8~port10 setup is done in a separate register
You are in the correct (UTF-8) encoding when you see:
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
e.g. week 3, 08 third month, 2017
But not if you see:
* $Date: 2017-03-08 15:13:58 +0800 (閫变笁, 08 涓夋湀 2017) $
rtl8367c/rtl8367c_asicdrv_lut.c should be read as UTF-8, despite having
some earlier Chinese text lost to GB18030 encoding.
Improves indexing and searches
Signed-off-by: Paul Donald <newtwen+github@gmail.com>
HW specifications:
* Mediatek MT7981A
* 256MB SPI-NAND
* 512MB DRAM
* Uplink: 1 x 10/100/1000Base-T Ethernet, Auto MDIX, RJ-45 with 802.3at
PoE (Built-in GBe PHY)
* LAN: 1 x 10/100/1000Base-T Ethernet, Auto MDIX, RJ-45 (Airoha EN8801SC)
* 1 Tricolor LED
* Reset button
* 12V/2.0A DC input
Installation:
Board comes with OpenWifi/TIP which is OpenWrt based, so sysupgrade can
be used directly over SSH.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Airoha EN8801SC PHY is a gigabit PHY used on Edgecore EAP111 so, include
the MTK driver with some cleanups.
Unfortunatelly, there is no specification sheet nor datasheet available
in order to demistify the magic PBUS writes and work on upstreaming
this driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Specification:
- MT7981 CPU using 2.4GHz and 5GHz WiFi (both AX)
- MT7531 switch
- 512MB RAM
- 128MB NAND flash with two UBI partitions with identical size
- 1 multi color LED (red, green, blue, white) connected via GCA230718
- 3 buttons (WPS, reset, LED on/off)
- 1 1Gbit WAN port
- 4 1Gbit LAN ports
Disassembly:
- There are four screws at the bottom: 2 under the rubber feets, 2 under the label.
- After removing the screws, the white plastic part can be shifted out of the blue part.
- Be careful because the antennas are mounted on the side and the top of the white part.
Serial Interface
- The serial interface can be connected to the 4 pin holes on the side of the board.
- Pins (from front to rear):
- 3.3V
- RX
- TX
- GND
- Settings: 115200, 8N1
MAC addresses:
- WAN MAC is stored in partition "Odm" at offset 0x81
- LAN (as printed on the device) is WAN MAC + 1
- WLAN MAC (2.4 GHz) is WAN MAC + 2
- WLAN MAC (5GHz) is WAN MAC + 3
Flashing via Recovery Web Interface:
- The recovery web interface always flashes to the currently active partition.
- If OpenWrt is flahsed to the second partition, it will not boot.
- Ensure that you have an OEM image available (encrypted and decrypted version). Decryption is described in the end.
- Set your IP address to 192.168.200.10, subnetmask 255.255.255.0
- Press the reset button while powering on the device
- Keep the reset button pressed until the LED blinks red
- Open a Chromium based and goto http://192.168.200.1 (recovery web interface)
- Download openwrt-mediatek-filogic-dlink_aquila-pro-ai-m30-a1-squashfs-recovery.bin
- The recovery web interface always reports successful flashing, even if it fails
- After flashing, the recovery web interface will try to forward the browser to 192.168.0.1 (can be ignored)
- If OpenWrt was flashed to the first partition, OpenWrt will boot (The status LED will start blinking white and stay white in the end). In this case you're done and can use OpenWrt.
- If OpenWrt was flashed to the second partition, OpenWrt won't boot (The status LED will stay red forever). In this case, the following steps are reuqired:
- Start the web recovery interface again and flash the **decrypted OEM image**. This will be flashed to the second partition as well. The OEM firmware web interface is afterwards accessible via http://192.168.200.1.
- Now flash the **encrypted OEM image** via OEM firmware web interface. In this case, the new firmware is flashed to the first partition. After flashing and the following reboot, the OEM firmware web interface should still be accessible via http://192.168.200.1.
- Start the web recovery interface again and flash the OpenWrt recovery image. Now it will be flashed to the first partition, OpenWrt will boot correctly afterwards and is accessible via 192.168.1.1.
Flashing via U-Boot:
- Open the case, connect to the UART console
- Set your IP address to 192.168.200.2, subnet mask 255.255.255.0. Connect to one of the LAN interfaces of the router
- Run a tftp server which provides openwrt-mediatek-filogic-dlink_aquila-pro-ai-m30-a1-initramfs-kernel.bin.
- Power on the device and select "7. Load image" in the U-Boot menu
- Enter image file, tftp server IP and device IP (if they differ from the default).
- TFTP download to RAM will start. After a few seconds OpenWrt initramfs should start
- The initramfs is accessible via 192.168.1.1, change your IP address accordingly (or use multiple IP addresses on your interface)
- Perform a sysupgrade using openwrt-mediatek-filogic-dlink_aquila-pro-ai-m30-a1-squashfs-sysupgrade.bin
- Reboot the device. OpenWrt should start from flash now
Revert back to stock using the Recovery Web Interface:
- Set your IP address to 192.168.200.2, subnetmask 255.255.255.0
- Press the reset button while powering on the device
- Keep the reset button pressed until the LED blinks red
- Open a Chromium based and goto http://192.168.200.1 (recovery web interface)
- Flash a decrypted firmware image from D-Link. Decrypting an firmware image is described below.
Decrypting a D-Link firmware image:
- Download https://github.com/RolandoMagico/firmware-utils/blob/M32/src/m32-firmware-util.c
- Compile a binary from the downloaded file, e.g. gcc m32-firmware-util.c -lcrypto -o m32-firmware-util
- Run ./m32-firmware-util M30 --DecryptFactoryImage <OriginalFirmware> <OutputFile>
- Example for firmware M30A1_FW101B05: ./m32-firmware-util M30 --DecryptFactoryImage M30A1_FW101B05\(0725091522\).bin M30A1_FW101B05\(0725091522\)_decrypted.bin
Flashing via OEM web interface is not possible, as it will change the active partition and OpenWrt is only running on the first UBI partition.
Controlling the LEDs:
- The LEDs are controlled by a chip called "GCA230718" which is connected to the main CPU via I2C (address 0x40)
- I didn't find any documentation or driver for it, so the information below is purely based on my investigations
- If there is already I driver for it, please tell me. Maybe I didn't search enough
- I implemented a kernel module (leds-gca230718) to access the LEDs via DTS
- The LED controller supports PWM for brightness control and ramp control for smooth blinking. This is not implemented in the driver
- The LED controller supports toggling (on -> off -> on -> off) where the brightness of the LEDs can be set individually for each on cycle
- Until now, only simple active/inactive control is implemented (like when the LEDs would have been connected via GPIO)
- Controlling the LEDs requires three sequences sent to the chip. Each sequence consists of
- A reset command (0x81 0xE4) written to register 0x00
- A control command (for example 0x0C 0x02 0x01 0x00 0x00 0x00 0xFF 0x01 0x00 0x00 0x00 0xFF 0x87 written to register 0x03)
- The reset command is always the same
- In the control command
- byte 0 is always the same
- byte 1 (0x02 in the example above) must be changed in every sequence: 0x02 -> 0x01 -> 0x03)
- byte 2 is set to 0x01 which disables toggling. 0x02 would be LED toggling without ramp control, 0x03 would be toggling with ramp control
- byte 3 to 6 define the brightness values for the LEDs (R,G,B,W) for the first on cycle when toggling
- byte 7 defines the toggling frequency (if toggling enabled)
- byte 8 to 11 define the brightness values for the LEDs (R,G,B,W) for the second on cycle when toggling
- byte 12 is constant 0x87
Comparison to M32/R32:
- The algorithms for decrypting the OEM firmware are the same for M30/M32/R32, only the keys differ
- The keys are available in the GPL sources for the M32
- The M32/R32 contained raw data in the firmware images (kernel, rootfs), the R30 uses a sysupgrade tar instead
- Creation of the recovery image is quite similar, only the header start string changes. So mostly takeover from M32/R32 for that.
- Turned out that the bytes at offset 0x0E and 0x0F in the recovery image header are the checksum over the data area
- This checksum was not checked in the recovery web interface of M32/R32 devices, but is now active in R30
- I adapted the recovery image creation to also calculate the checksum over the data area
- The recovery image header for M30 contains addresses which don't match the memory layout in the DTS. The same addresses are also present in the OEM images
- The recovery web interface either calculates the correct addresses from it or has it's own logic to determine where which information must be written
Signed-off-by: Roland Reinl <reinlroland+github@gmail.com>
