Update header file appropriately and disable read for ownership
Note that the FIQ support implements a workaround that provides a performance
boost over the traditional upstream workaround which ensures cache lines
are exclusive on driver CPU using 'read for ownership'.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/config-3.3 | 2 +-
target/linux/cns3xxx/patches-3.3/460-cns3xxx_fiq_support.patch | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
SVN-Revision: 33827
- properly check for the link up condition in the phylib adjust callback
- do not assign skb->dev, eth_type_trans() already does it
- handle skb allocation failures in the refill path
SVN-Revision: 33780
Commit r33248 introduced a regression by passing the board name plus
'board=' in the third argument. The board name string has to be put
into the image as identifier of the image type.
[juhosg: fix OpenMesh template instead of use of string substitution]
Signed-off-by: Marek Lindner <lindner_marek@yahoo.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 33767
Handle the different vlynq device versions, and make the vlynq code more
in line with the original vlynq implementation.
Patch from Daniel Gimpelevich.
SVN-Revision: 33755
At least devices without a switch present on the MDIO bus still get a valid
link and work as expected (such as the Linksys WAG54Gv2).
SVN-Revision: 33751
The Laguna boards do not use all the same pins for SDHCI as the Cavium
reference board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33684
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too. I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.
This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33683
This allows sysupgrade for devices such as the Gateworks Avila/Cambria
product families based on the ixp4xx using the redboot bootloader with
combined FIS directory and RedBoot config partitions on larger FLASH
devices with larger eraseblocks.
This second iteration of this patch addresses previous issues:
- whitespace breakage fixed
- unlock in all scenarios
- simplification and fix logic bug
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33681
Enabling OPTIMIZE_FOR_SIZE cuts the kernel binary down by 50K which is
critical for some small-footprint boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33679
Several new features for newer boards:
- add additional UARTs present on some boards
- add additional LEDs present on some boards
- add HSS audio device codec present on some boards
- add support for GSC present on some boards
- add per model setup support for newer boards
- set FLASH window per-model for boards with larger FLASH
Some fixes:
- add IRQ mapping for additional PCI devices (USB Host)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33647
Several new features for newer boards:
- add irq mapping for additional devices
- add platform data for i2c bus to SFP modules
- add additional UARTs present on some boards
- increased R/W delay for expansion bus UARTs
- add additional LEDs present on some boards
- add GPIO exports and configuration
- add ENET switch config present on some boards
- add support for GSC present on some boards
- added per model setup support for newer boards
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33644
Before it was tried to initialize the deactivated PCIe core in client
mode, but this causes the SoC to hang. Just do not initialize it at all
and ignore the core it is not working and nothing is connected to it
when the specific bit is set in the boardflags.
SVN-Revision: 33620
The new version of the ALL0256N now got 8MB SPI NOR flash instead of 4MB.
In order to expose the whole amount of flash, add another image which contains
the corresponding GENERIC_8M mtdparts.
[juhosg: change suffix from '8m' to '8M']
Patch by: Daniel Golle <dgolle@allnet.de>
SVN-Revision: 33614
Sometimes the PCIe card indicates that it has a sprom somewhere and we
are able to read the memory region, but it is empty and not valid. In
these cases we should try to use the fallback sprom as a last chance.
SVN-Revision: 33601
The chip common and the PCIe code are accessing the sprom struct which
is not filled when these cores are initialized. Fix this by adding an
early initialize and fill the sprom struct before accessing it in other
code.
SVN-Revision: 33600
The bcma based SoCs with a ieee80211 core on the SoC and an other
connected via PCIe or USB store the sprom for the SoC with a sb/1/
prefix. The SoC with just one wifi core do not use prefixes. The
BCM4706 do not use a prefix for the SoC part at all, because the prefix
is the path to the ieee80211 core and there is non on the BCM4706.
SVN-Revision: 33597
Resolves an issue where isochronouse USB would cause the driver to hang as
well as scheduling issues.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33579
This feature was experimental in old kernels but
that flag has been removed in 2.6.36. Additionally,
the option is enabled by default since then.
See: http://www.spinics.net/lists/linux-usb/msg31993.html
SVN-Revision: 33574
For cns3xxx SCU_CONFIGURATION always shows multipe cores but SCU_CPU_STATUS
shows which ones are active.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33566
