Commit Graph

456 Commits

Author SHA1 Message Date
Olliver Schinagl
44e0785285 realtek: Migrate to upstream generic MIPS addresses
Upstream generic MIPS uses 0x80100000 and 0x80100400 for the LOADADDR
and ENTRY addresses. As we do not want to diverge from upstream and
patch upstream when not needed, adjust our addresses as well to be
future proof.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
2023-01-05 21:59:20 +01:00
Olliver Schinagl
9260027535 realtek: Migrate to libdeflate
Libdeflate is a more advanced gzip compressor, which allows for faster
decompression, higher compression speed (factor 3-4), while being fully
gzip compatible.

Some comparison
gzip    | libdeflate-gzip | delta  | image [openwrt-realtek-rtl839x-*]
--------+-----------------+--------+-----------------------------------------------
6589174 | 6298794         | 290380 | d-link_dgs-1210-52-initramfs-kernel.bin
6291632 | 6029488         | 262144 | d-link_dgs-1210-52-squashfs-factory_image1.bin
6292270 | 6030128         | 262142 | d-link_dgs-1210-52-squashfs-sysupgrade.bin
6589142 | 6298760         | 290382 | zyxel_gs1900-48-initramfs-kernel.bin
6292264 | 6030122         | 262142 | zyxel_gs1900-48-squashfs-sysupgrade.bin

and changing lzma to (libdeflate-)gzip on existing rtl930x target:
gzip    | libdeflate-gzip | delta  | image [openwrt-realtek-rtl930x-*]
--------+-----------------+--------+--------------------------------------
6816230 | 6510382         | 305848 | zyxel_xgs1250-12-initramfs-kernel.bin

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Sander Vanheule <sander@svanheule.net>
2023-01-02 10:18:44 +01:00
Olliver Schinagl
c9a7c00f80 realtek: Disable boston clock
We are not on the 'boston' platform so no point in having that clock
driver enabled.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2023-01-01 22:31:20 +01:00
Sander Vanheule
045baca10b realtek: deduplicate GS1900 recipes
ZyXEL GS1900 devices with SoCs from both the RTL838x and RTL839x
families share the same image structure and size of the firmware
partition. Additionally, the GS1900-48 recipe provided a parameter for
the zyxel-vers command, but this parameter is not used. Deduplicate the
recipes by moving it to target/linux/realtek/image/common.mk.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-28 22:44:10 +01:00
Sander Vanheule
1e13081064 realtek: fix GS1900-48 firwmare partition
The listed partition size doesn't match the original partition size, and
actually overlaps with the following partition. The partition node name
for the "firmware" partition also has an extra 'b' compared to the
partition offset.

Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-28 22:44:10 +01:00
Sander Vanheule
80be0fea03 realtek: fix ZYXELS_VERS for GS1900-48
The GS1900-48 firmware image is identified by the 'AAHN' ID, while the
GS1900-48HP is identified by 'AAHO' [1]. The latter was used, resulting
in the following error message when upgrading via the stock web UI:

  Device only can support firmware from V1.00(AAHN.0) and later version

Fix image generation by using the correct ID.

[1] https://download.zyxel.com/GS1900-48/firmware/GS1900-48_2.70(AAHN.3)C0_2.pdf

Link: https://forum.openwrt.org/t/146533
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Suggested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-28 22:44:10 +01:00
Sander Vanheule
ab8a5f2ea0 realtek: fix default image generation
While cleaning up the makefiles for the realtek target, the order of the
default image generating commands was accidentally changed. This caused
the image signature to end up somewhere in the middle, misaligning the
rootfs. As a result, sysupgrade couldn't verify upgrade images anymore,
and devices end up in a boot loop due to the unaligned (and not found)
rootfs.

Fixes: 94d8b4852b ("realtek: Cleanup Makefiles")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-28 22:44:10 +01:00
Birger Koblitz
e143e27c8c realtek: Fix reset register access
The reset register on RTL93xx not merely have bits to execute
a reset of a hardware component, but also configuration bits for
reset procedures. Keep them during executing a reset.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[backport to 5.10 kernel]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-28 16:53:56 +01:00
Olliver Schinagl
0a83889e89 realtek: Reduce variable scopes
Linus prefers to have loop initializers nice and tightly scoped. In
OpenWRT this has been possible since 41a1a652fb ("kernel: backport
gnu11 upgrade").

This patch cleans up variable scope while trying to do the above for
'simple for loops'.

This cleans up and simplifies some functions and code, and pulls in
variables to a smaller scope.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-12-27 16:33:15 +01:00
Olliver Schinagl
94d8b4852b realtek: Cleanup Makefiles
Our current Makefiles a little bit messy and can be improved somewhat,
both in whitespace and in style.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-12-27 16:33:15 +01:00
Olliver Schinagl
0a931767cf realtek: Replace C++ style comments
The only exception to C++ style comments are SPDX license identifier
markers at the start of C files (even headers have C style markers).

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-12-27 16:33:01 +01:00
Olliver Schinagl
758c88b969 realtek: Whitespace and codestyle cleanup
Fix some ugly whitepsaces and codestyle issues around the realtek sources.

While this is by no means perfect, it catches what it caught.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-12-27 16:31:48 +01:00
Jan Hoffmann
2c40359c5c realtek: add cond_resched to loops accessing the FDB table
A full loop accessing all FDB entries can take several milliseconds
(on RTL839x about 20 ms), so give other kernel tasks a chance to run.
This is especially important for rtl83xx_port_fdb_dump which is itself
called in a loop for all ports by the kernel.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-12-27 16:29:57 +01:00
Jan Hoffmann
ae0a3f88ac realtek: restructure rtl_table_read/write
These two functions are identical apart from writing different values to
the read/write bit. Create a new function rtl_table_exec to reduce code
duplication.

Also replace the unbounded busy-waiting loop. The new implementation may
sleep, but as the hardware typically responds before the first poll, any
callers doing many table accesses still need to make sure not to block
other kernel tasks themselves.

So far, polling timeout errors are only handled by logging an error, but
a return value is added to allow proper handling in the future.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-12-27 16:29:57 +01:00
Jan Hoffmann
9aa123d778 realtek: simplify log messages in rtl83xx_mdio_probe
This function currently prints three messages for every switch port at
KERN_INFO level. This takes a considerable amount of time during bootup
and can even trigger an external watchdog.

Replace these log messages by a single one at KERN_DEBUG level.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-12-27 16:29:57 +01:00
Jan Hoffmann
c94ca63ed4 realtek: don't set L2LEARNING flag in rtl83xx TX header
As learning for the CPU port is now disabled globally, the bit in the
TX header doesn't have any effect anymore. Remove it to make the header
consistent with the global configuration.

Originally, this change was intended to be applied before commit
eb456aedfe ("realtek: use assisted learning on CPU port"), which is
why the commit message incorrectly mentions that the TX header already
disables learning.

The reason for disabling learning on the CPU port in the first place is
that it doesn't work correctly when packets are trapped to the CPU and
then forwarded by the CPU to other ports. In that case, the switch would
incorrectly learn the CPU port as source. An example that triggered this
issue are Multicast Listener Reports and IGMP membership reports.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-12-27 16:29:39 +01:00
Olliver Schinagl
f649a7b5f3
realtek: 5.15: Fix incorrect switch patches
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.

See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-12-24 11:56:21 +01:00
Olliver Schinagl
113fd5b93b
realtek: 5.10: Fix incorrect switch patches
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.

See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-12-24 11:56:21 +01:00
John Audia
e900822326 kernel: bump 5.15 to 5.15.84
All patches automatically rebased

Build system: x86_64
Build-tested: bcm2711/RPi4B
Run-tested: bcm2711/RPi4B

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-12-19 23:51:10 +01:00
INAGAKI Hiroshi
88db7461cf realtek: add Linux Kernel 5.15 as testing version
Add Linux Kernel 5.15 support for testing.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[APRESIA ApresiaLightGS120GT-SS, Panasonic Switch-M24eG PN28240K, Switch-M48eG PN28480K]
Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com>
TP-Link TL-SG2008P
Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[D-Link DGS-1210-20, DGS-1210-52, Zyxel XGS1010-12]
Tested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[Zyxel XGS1250-12]
Tested-by: Lucian Cristian <lucian.cristian@gmail.com> # Zyxel
[HPE 1920-8G, 1920-48G]
Tested-by: Jan Hoffmann <jan@3e8.eu>
2022-12-15 20:54:12 +01:00
INAGAKI Hiroshi
69055a5412 realtek: enable needs_standalone_vlan_filtering on DSA driver in 5.15
To configure VLAN 0, enable needs_standalone_vlan_filtering option
of dsa_switch struct.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-12-15 20:54:03 +01:00
INAGAKI Hiroshi
109962d8bf realtek: update dsa.c of DSA driver for 5.15
- rtl83xx_vlan_filtering()

  "struct switchdev_trans *trans" parameter was removed[1] and
  "struct netlink_ext_ack *extack" was added[2].

[1]: https://www.spinics.net/lists/netdev/msg712250.html
[2]: https://www.spinics.net/lists/netdev/msg722496.html

- rtl83xx_vlan_add/del()

  vlan->vid_begin and vlan->vid_end were removed and vlan->vid was
  added[3].

[3]: https://www.spinics.net/lists/netdev/msg712248.html

- rtl83xx_vlan_prepare()

  "port_vlan_prepare" member was removed from "dsa_switch_ops" struct
  in dsa.h[4] and vlan_prepare function should be called from vlan_add
  function. Also, change return type of vlan_add function to int.

[4]: https://www.spinics.net/lists/netdev/msg712252.html

- rtl83xx_port_mdb_add()

  "port_mdb_prepare" member in "dsa_switch_ops" struct was removed and
  preparation need to be done in the function of "port_mdb_add" member
  instead. And also, int type need to be returned on "port_mdb_add"
  member[5].

[5]: https://www.spinics.net/lists/netdev/msg712251.html

- rtl83xx_port_pre_bridge_flags(), rtl83xx_port_bridge_flags()

  The current "port_pre_bridge_flags" member and "port_bridge_flags"
  member in "dsa_switch_ops" in dsa.h has flags of
  "struct switchdev_brport_flags" type instead[6], so adjust to it.
  And, the changed features are passed by flags.mask[7] in
  rtl83xx_port_bridge_flags(), so check it before calling function
  to enable/disable fieature.

[6]: https://lore.kernel.org/lkml/20210212151600.3357121-7-olteanv@gmail.com/
[7]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e18f4c18ab5b0dd47caaf8377c2e36d66f632a8c

Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[shorten final return statement of rtl83xx_port_mdb_add()]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-15 20:52:40 +01:00
INAGAKI Hiroshi
1f153558a3 realtek: update platform support for 5.15
- fw_passed_dtb and others were replaced to get_fdt() function[1]
- __appended_dtb defined by asm/bootinfo.h[2]

[1]: https://www.spinics.net/lists/linux-mips/msg03332.html
[2]: https://www.spinics.net/lists/linux-mips/msg03332.html

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-12-15 20:52:40 +01:00
INAGAKI Hiroshi
f3a9975549 realtek: refresh config-5.15 in all subtargets
Refresh config-5.15 in all subtargets by kernel_menuconfig.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-12-15 20:52:40 +01:00
INAGAKI Hiroshi
aa528eec73 realtek: refresh patches in 5.15
Adjust patches for kernel 5.15.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-12-15 20:52:40 +01:00
INAGAKI Hiroshi
23881c91e5 realtek: drop patches of upstreamed fix and changes from 5.15
- 007-5.16-gpio-realtek...: upstreamed on 5.16 and backported to 5.15.3
- 708-brflood-spi.patch   : upstreamed
- 709-lag-offloading.patch: upstreamed
- 713-v5.12-net-dsa-...   : upstreamed and some implementations are
                            replaced

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-12-15 20:52:40 +01:00
INAGAKI Hiroshi
a9d5a8bc79 realtek: drop patches of upstreamed drivers from 5.15
The following drivers were upstreamed and available on 5.15, so drop
from OpenWrt tree.

- realtek-otto-gpio (5.13)
- realtek-rtl-spi (5.12)
- realtek-rtl-intc (5.12)

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-12-15 20:52:40 +01:00
INAGAKI Hiroshi
8fb15ea52a realtek: copy dts/files/patches/configs for 5.15
Copy dts/files/patches/configs from 5.10 to 5.15.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[refresh with updated DGS-1210 dts files]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-15 20:52:09 +01:00
Jan-Niklas Burfeind
dbc93d280c realtek: update GPIO bindings for DGS-1210-10P
add three missing LEDs
 - PoE-Max
 - Link/Act
 - PoE

add two missing buttons
 - mode
 - reset

The last was dropped in
commit 61a3d0075b ("realtek: update GPIO bindings in the dts files in dts-5.10")

Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
2022-12-09 00:13:51 +01:00
Andreas Böhler
3e7e4d0b97 realtek: d-link: add support for dgs-1210-28mp-f
General hardware info:
----------------------

D-Link DGS-1210-28MP rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC @ 500MHz,
DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 370W.

Power over Ethernet:
--------------------

The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU.
In order to enable PoE, the realtek-poe package is required. It is
installed by default, but currently it requires the manual editing of
/etc/config/poe. Keep in mind that the port number assignment does not
match on this switch, alway 8 ports are in reversed order: 8-1, 16-9 and
24-17.

LEDs and Buttons:
-----------------

On stock firmware, the mode button is supposed to switch the LED indicators
of all port LEDs between Link Activity and PoE status. The currently
selected mode is visualized using the respective LEDs. PoE Max indicates
that the maximum PoE budget has been reached.
Since there is currently no support for this behavior, these LEDs and
the mode button can be used independently.

Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.

Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd

OEM installation from Web Interface:
------------------------------------

  1. Make sure you are booting using OEM in image 2 slot. If not, switch to
     image2 using the menus
        System > Firmware Information > Boot from image2
        Tools > reboot
  2. Upload image in vendor firmware via Tools > Backup / Upgrade
     Firmware > image1
  3. Toogle startup image via System > Firmware Information > Boot from
     image1
  4. Tools > reboot

Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:

Boot initramfs image from U-Boot:
---------------------------------

  1. Press Escape key during `Hit Esc key to stop autoboot` prompt
  2. Press CTRL+C keys to get into real U-Boot prompt
  3. Init network with `rtk network on` command
  4. Load image with `tftpboot 0x8f000000
     openwrt-rtl838x-generic-d-link_dgs-1210-28mp-f-initramfs-kernel.bin`
     command
  5. Boot the image with `bootm` command

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-12-08 21:51:43 +01:00
Jan-Niklas Burfeind
a5873ad675 realtek: fix dell typo
should be add/delete or abbreviated add/del

Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-12-01 22:49:23 +01:00
Luiz Angelo Daros de Luca
ed9bd9824a realtek: refactor keep vlan tag setup, fix tagged forwarding
The code in dsa.c:rtl83xx_port_enable() was trying to set
vlan_port_tag_sts_ctrl while dealing with differences between SoCs.
However, not only that register has a different address, the register
structure and even the 2-bit value semantic changes for each SoC.

The vlan_port_tag_sts_ctrl field was dropped and converted into a
vlan_port_keep_incoming_tag_set() function that abstracts the different
between SoCs. The macro referencing that register migrated to the SoC
specific c file as it will be privately used by each file.

All magic numbers were converted into macros using BITMASK and
FIELD_PREP.

The vlan_port_tag_sts_ctrl debugfs was dropped for now as it is already
broken for rtl93xx. The best place for SoC specific code might be in each
respective c file and not in if/else clauses.

The final result is:

rtl838x: set ITAG_STS=TAGGED, same as before
rtl839x: set ITAG_STS=TAGGED instead of IGR_P_ITAG_KEEP=0x1, fixing
	 forwarding of tagged packets
rtl930x: set EGR_ITAG_STS=TAGGED instead of IGR_P_ITAG=0x1, possibly
	 fixing forwarding of tagged packets
rtl931x: set EGR_ITAG_STS=TAGGED instead of OTPID_KEEP=0x1, possibly
         fixing forwarding of tagged packets

Without (EGR_)ITAG_STS=TAGGED, at least for rtl839x, forwarded packets
will drop the vlan tag while packets from the CPU will still have the
correct tag.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-12-01 22:15:55 +01:00
Olliver Schinagl
59542c9ac9 realtek: Fix rtl930x speed status accessor
The rtl930x speed status registers require 4 bits to indicate the speed
status. As such, we want to divide by 8. To make things consistent with
the rest of this code, use a bitshift however.

This bug probably won't affect many users yet, as there aren't many
rtl930x switches in the wild yet with more then 10 ports, and thus a
low-impact bugfix.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[also fix port field extraction]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-12-01 22:11:06 +01:00
Luiz Angelo Daros de Luca
1ee635c561 realtek: fix typo in debug message
vid_end was mentioned twice.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-11-05 16:27:21 +01:00
Sander Vanheule
75c576d4c4 realtek: mark clock source as continuous
After replacing the R4K event timer and clock source with the new
Realtek Otto timer, performance for RTL839x devices was severely
impacted, as reported by Hiroshi.

Research by Markus showed that after commit 4657a5301e ("realtek:
avoid busy waiting for RTL839x PHY read/write"), the ethernet driver
could only update a phy once per timer interval, which also heavily
impacted boot time. On e.g. a Zyxel GS1900-48, this added around a
minute to the time to fully initialise the switch.

By marking the otto clocksource as continuous, the kernel enables it to
be used for high resolution timers. This allows readx_poll_timeout() to
sleep for less than one system timer interval, reducing system dead
time.

Link: https://github.com/openwrt/openwrt/issues/11117
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Cc: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
2022-11-01 09:13:11 +01:00
Rosen Penev
3b93651072 target/realtek: use netif_receive_skb_list
Small performance improvement on rx.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
2022-11-01 09:09:24 +01:00
Olliver Schinagl
f4849c0ab7 realtek: Fix CRC offloading for rtl83xx
In rtl83xx_set_features we set bit 3 to enable, and bit 4 to disable
checksuming. Looking at rtl93xx_set_features we however see that for
both enable and disable the same bit is used (bit 4). This can't be
right, especially as bit 4 for rtl83xx seems to be Collision threshold
occupying 2 bits. Change this to make this more logical.

Fixes: 9e8d62e421 ("realtek: enable CRC offloading")
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-10-29 11:18:04 +02:00
Jan Hoffmann
eb456aedfe realtek: use assisted learning on CPU port
L2 learning on the CPU port is currently not consistently configured and
relies on the default configuration of the device. On RTL83xx, it is
disabled for packets transmitted with a TX header, as hardware learning
corrupts the forwarding table otherwise. As a result, unneeded flooding
of traffic for the CPU port can already happen on some devices now. It
is also likely that similar issues exist on RTL93xx, which doesn't have
a field to disable learning in the TX header.

To address this, disable hardware learning for the CPU port globally on
all devices. Instead, enable assisted learning to let DSA write FDB
entries to the switch.

For now, this does not sync local/bridge entries to the switch. However,
support for that was added in Linux 5.14, so the next switch to a newer
kernel version is going to fix this.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-26 09:59:38 +02:00
Jan Hoffmann
2088e440b1 realtek: set up L2 table entries properly
Initialize the data structure using memset to avoid the possibility of
writing garbage values to the hardware.

Always set a valid entry type, which should fix writing unicast entries
on RTL930x.

For unicast entries, set the is_static flag to prevent the switch from
aging them out.

Also set the rvid field for unicast entries. This is not strictly
necessary, as the switch fills it in automatically from a non-zero vid.
However, this makes the code consistent with multicast entry setup.

While at it, reorder the statements and fix some style issues (double
space, comma instead of semicolon at end of statement). Also remove the
unneeded priv parameter and debug print for the multicast entry setup
function.

Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-26 09:59:24 +02:00
Christian Marangi
a31b598590
realtek: 5.10: refresh kernel patches
Refresh kernel patches for realtek 5.10 kernel

Refreshed patch:
- 300-mips-add-rtl838x-platform.patch

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2022-10-25 04:56:16 +02:00
Sander Vanheule
9f6cbc78cd realtek: consistently flood RMA frames
The switches support different actions for incoming ethernet multicast
frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The
current code will set the 2-bit action field to FLOOD (0x3) for most
classes, but the highest bit is always unset for the relevant control
registers. This means the DROP (0x1) action being used for these
classes; whatever class the MSB happens to be in.

For RTL838x, this results in {20,23-2F} frames being dropped, instead of
flooding all ports. On other switch generations, {0F,1F,2F} frames are
dropped. This is inconsistent, and appears to be a mistake. Remove this
inconsistency by flooding all multicast frames with RMA addresses.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Sander Vanheule
039e5be4af realtek: remove RTL839x path in RTL838x multicast
The multicast setup function rtl838x_eth_set_multicast_list() checks if
the current SoC is a RTL839x family device. However, the function is
only included in the RTL838x ops table, so this path should never be
taken, making this dead code. rtl839x_eth_set_multicast_list() is
already present in the RTL839x ops table, so it should be safe to remove
this branch.

While touching the code, also re-sort the functions to match sorting
elsewhere, with rtl838x coming before rtl839x.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Jan Hoffmann
19b86658b7 realtek: reduce excessive logging for FDB operations
Currently several messages at KERN_INFO level are printed for every FDB
del/dump operation. This can cause a significant slowdown for example
while using "bridge fdb", and may even trigger a watchdog.

Remove most of these log messages, as the new L2 table debugfs node
should be a good replacement. Change the remaining messages to
KERN_DEBUG level.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-23 22:33:08 +02:00
Jan Hoffmann
ae9487c535 realtek: add debugfs node for L2 table
This allows to view all unicast and multicast entries that are currently
in the L2 hash table and the CAM.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-23 22:33:08 +02:00
Jan Hoffmann
4657a5301e realtek: avoid busy waiting for RTL839x PHY read/write
Switch to a polling implementation similar to the one for RTL838x, to
allow other kernel tasks to run while waiting.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
b295c7140b realtek: disable otto timer for RTL93xx targets
The new timer is not yet ready for all targets. Avoid interactive
questions during build

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[rename symbol to CONFIG_REALTEK_OTTO_TIMER]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
beb5b07943 realtek: timer driver: activate for RTL839X devices
Use the	new timer driver for the RTL839X devices and remove the
no longer needed modules.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
ec675fb744 realtek: timer driver: activate for RTL838X devices
Use the new timer driver for the RTL838X devices. Remove the no
longer needed modules.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
5c677b2298 realtek: timer driver: documentation
Provide some helpful information about the devicetree configuration of
our new driver

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct compatible order in examples]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
3cc8011171 realtek: resurrect timer driver
Now that we provide a clock driver for the Reltek SOCs the CPU frequency might
change on demand. This has direct visible effects during operation

- the CEVT 4K timer is no longer a stable clocksource
- after CPU frequencies changes time calculation works wrong
- sched_clock falls back to kernel default interval (100 Hz)
- timestamps in dmesg have only 2 digits left

[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ...
[    0.060000] pid_max: default: 32768 minimum: 301
[    0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build
[    0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ...

Looking around where we can start the CEVT timer for RTL930X is a good basis.
Initially it was developed as a clocksource driver for the broken timer in that
specific SOC series. Afterwards it was shifted around to the CEVT location,
got SMP enablement and lost its clocksource feature. So we at least have
something to copy from. As the timers on these devices are well understood
the implementation follows this way:

- leave the RTL930X implementation as is
- provide a new driver for RTL83XX devices only
- swap RTL930X driver at a later time

Like the clock driver this patch contains a self contained module that is SOC
independet and already provides full support for the RTL838X, RTL839X and
RTL930X devices. Some of the new (or reestablished) features are:

- simplified initialization routines
- SMP setup with CPU hotplug framework
- derived from LXB clock speed
- supplied clocksource
- dedicated register functions for better readability
- documentation about some caveats

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove unused header includes, remove old CONFIG_MIPS dependency, add
REALTEK_ prefix to driver symbol]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
INAGAKI Hiroshi
629f2de1a7 realtek: cleanup rtl83{8x,9x}_enable_learning/flood
In *_enable_learning() only address learning should be configured, so
remove enabling forwarding. Forwarding is configured by the respective
*_enable_flood() functions.

Clean up both functions for RTL838x and RTL839x, and fix the comment on
the number of entries.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash RTL838x, RTL839x changes]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:03 +02:00
INAGAKI Hiroshi
b11b56e8a8 realtek: swap *_phylink_mac_link_down() contents
Fix the (accidentally?) swapped contents of
rtl83xx_phylink_mac_link_down() and rtl93xx_phylink_mac_link_down().

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
ff307f52f5 realtek: fix place of fdb/mdb info messages
Those messages should be printed when entry was found (idx >= 0). Move
them to the right place to not print invalid entry indices.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amden commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
3834e72fa3 realtek: add missing of.h include in phy driver
of.h is required for of_property_read_u32().

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
04cca345df realtek: fix use of uninitialized sds_mode
The initial state of sds_mode in rtl9300_force_sds_mode() is null and it
will be configured in switch-case. So print message after it.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
27a580df4a realtek: use MIPS fw_init_cmdline()
Use the generic function of MIPS in Linux Kernel instead of open coding
our own initialisation.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
5b37e3245d realtek: update SMP-related calls in prom_init()
The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it
will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects
this symbol, so the family check is redudant.

Furthermore, mips_cm_probe() is already called from setup_arch() in
mips/kernel/setup.c before prom_init(), and as such is not required.

Also move mips_cpc_probe() to run just before registering SMP ops.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash SMP change commits, reword commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
This patch only really has an impact on the rtl931x subtarget, which has
no devices. Noboby is currently set up to test these patches either, but
the end result is closer to MIPS_GENERIC, so I do not expect it to cause
issues.
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
9b53a29a58 realtek: separate lock of RTL8231 from phy driver
RTL8231 and ethernet phys are not on the same bus, so separate the lock
to each own to cut off the unnecessary dependency.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-10-08 11:05:02 +02:00
John Audia
eed0a31b90 kernel: bump 5.10 to 5.10.146
All patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-10-02 20:21:55 +02:00
Sander Vanheule
918e774658 realtek: use correct CAUSEF_DC macro in prom.c
The workaround for an already-enabled R4K timer used a non-existent
macro CAUSE_DC. Fix compiling by using the actual macro CAUSEF_DC.

Fixes: b7aab19585 ("realtek: SMP handling of R4K timer interrupts")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-01 09:56:54 +02:00
Markus Stockhausen
b7aab19585 realtek: SMP handling of R4K timer interrupts
Until now there has been no good explanation why we mess with the R4K
timer on SMP. After extensive testing and looking at the SDK code it
becomes clear what it is all about.

When we disable the CEVT_R4K module (we will do with the new timer
driver) the R4K timer hardware still fires interrupts on the secondary
CPU. To get around this we have two options:

- Disable IRQ 7
- Stop the counter completely

This patch selects option two because this is the root of evil.. To be
on the safe side we will do it only in case the CEVT_R4K module is
disabled.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-10-01 09:22:32 +02:00
Markus Stockhausen
2b12da1313 realtek: fix SMP startup
The scope of the SMP startup structure is wrong. It is created on the
stack and not as a global variable. This can lead to startup failures.

Fixes: 3f41360eb7 ("realtek: use upstream recommendation for CPU start")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de
2022-10-01 09:22:32 +02:00
Olliver Schinagl
f1f97db627
realtek: Convert incorrect v5.10 patches
OpenWRT's developer guide prefers having actual patches so they an be
sent upstream more easily.

However, in this case, Adding proper fields also allows for `git am` to
properly function. Some of these patches are quite old, and lack much
traceable history.

This commit tries to rectify that, by digging in the history to find
where and how it was first added.

It is by no means perfect and also shows some patches that should have
been long gone.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-10-01 02:47:57 +02:00
Felix Fietkau
36f2ab4bfd kernel: move kernel image cmdline hack to the octeon target
It is the only remaining user of this hack

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2022-09-30 13:13:51 +02:00
Christian Marangi
165b66d910
realtek: rtl931x: fix missing CONFIG_COMMON_CLK_REALTEK config flag
When the realtek clock driver was introduced, CONFIG_COMMON_CLK_REALTEK
was not correctly disabled for other subtarget. Add the missing config
flag to fix compilation error on buildbot.

Fixes: 4850bd887c ("realtek: add RTL83XX clock driver")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2022-09-28 01:15:47 +02:00
Jan Hoffmann
d924a75be3 realtek: fix RTL839x egress tag for ports >= 32
Don't overwrite AS_DPM and L2LEARNING flags when dest_port is >= 32.

Fixes: 1773264a0c ("realtek: correct egress frame port verification")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-09-25 20:53:24 +02:00
John Audia
eff4f8b2f0 kernel: bump 5.10 to 5.10.144
All patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-09-22 12:46:55 +02:00
Markus Stockhausen
3f41360eb7 realtek: use upstream recommendation for secondary CPU start
Currently we fix interrupts/timers for the secondary CPU by patching
vsmp_init_secondary(). Get a little bit more generic and use the
upstream recommended way instead. Additionally avoid a check around
register_cps_smp_ops() because it does that itself.

See https://lkml.org/lkml/2022/9/12/522

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-18 20:38:56 +02:00
Markus Stockhausen
bcb5d6b21b realtek: avoid wrong interrupt routing
The interrupt controller depends on two control registers. GIMR enables
or disables interrupts and IRRx routes these to MIPS CPU interrupts 2-7.
Wiki currently states "A value of '0' (in IRRx) disconnects this input from
the output line, independent of the line's setting in GIMR."

Contrary to normal intuition this statement DOES NOT mean, that interrupts
can be disabled by IRRx alone. The sad truth was discovered by enabling
SMP for an Zyxel XGS1010 on the 930x target. It shows that driver and
interrupts behave as follows:

- Timer 0 interrupt 7 has active routing to CPU0 and no routing to CPU1
- Timer 1 interrupt 8 has no routing to CPU0 and active routing to CPU1
- Unmasking (enabling) interrupts writes 1 bits to all GIMR registers
- Masking (disabling) interrupts writes 0 bits to both GIMR registers

During operation we can encounter a situation like

- GIMR bit for a interrupt/CPU combination is set to enabed (=1)
- IRRx routing bits for a interrupt/CPU combination are set to disabed (=0)

This setting already allows the hardware to fire interrupts to the target
CPU/VPE if the other CPU/VPE is currently busy. Especially for CPU bound
timer interrupts this is lethal. If timer interrupt 7 arrives at CPU1 and
vice versa for interrupt 8 the restart trigger gets lost. The timer dies
and a msleep() operation in the kernel will halt endlessly.

Fix this by tracking the IRRx active routing setting in a new bitfield with
0="routing active" and 1="no routing". Enable interrupts in GIMR only
for a interrupt & CPU if routing is active. Thus we have

- GIMR = 0 / IRRx = 0 -> everything disabled
- GIMR = 1 / IRRx > 0 -> active and normal routing
- GIMR = 0 / IRRx > 0 -> masked (disabled) with normal routing
- GIMR = 1 / IRRx = 0 -> no longer possible

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-18 20:38:56 +02:00
Sander Vanheule
fe5a2f334f realtek: use Device prefix for common recipes
The Build prefix is used for image build commands, while the Device
prefix should be used for base recipes for devices. Apply the same
naming convention here.

While touching the file, also fix the mixed indentation.

Suggested-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-18 10:12:19 +02:00
Olliver Schinagl
d2fa68379f realtek: move Netgear recipe to subtarget Makefile
There seems to be no reason to have the Netgear switches as part of
the main Makefile. Move it to its subtarget-specific Makefile since
it is only applicable there.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[update commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-17 22:27:32 +02:00
Sander Vanheule
51ecfb086c realtek: move hpe_1920 recipe to common.mk
Currently supported HPE 1920 devices all have an RTL838x SoC, but there
are larger switches with RTL839x SoCs, although currently not supported.
Move the build recipe to common.mk so the larger devices can also make
use of the recipe, while moving it out of the main Makefile.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-17 22:20:32 +02:00
Sander Vanheule
9338c09ecb realtek: merge duplicated DGS-1210 recipes
The D-Link DGS-1210 device series currently has supported devices with
both RTL838x and RTL839x SoCs. An image build recipe has been defined in
both subtarget makefiles, but these are mostly identical, save for the
SOC variable.

Move the SOC variable from the DGS-1210 build recipes to the applicable
devices, and put the remaining duplicate code in a shared Makefile.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-17 22:12:35 +02:00
Markus Stockhausen
e04e821471 realtek: add support for DGS-1210-52
Hardware specification
----------------------

* RTL8393M SoC, 1 MIPS 34Kc core @ 700MHz
* 128MB DRAM
* 32MB NOR Flash
* 48 x 10/100/1000BASE-T ports
  - 6 x External PHY with 8 ports (RTL8218D)
* 4 x Gigabit RJ45/SFP Combo ports
  - External PHY with 4 SFP ports (RTL8214FC)
* Power LED
* Reset button on front panel
* UART (115200 8N1) via unpopulated standard 0.1" pin header marked J14

The gpio-restart node is not required but it does reset the switch.

TODO: The 4 combo ports attached to the RTL8214FC are not detect
properly. Linux kernel reports 49 and 50 as "External RTL8393 SERDES"
and 51 and 52 as "RTL8218B (external)". Those ports only work if
u-boot initialize it (for example, loading initramfs image using one
of those ports). A patch to PHY detection is needed for full support.

The firmware recovery using U-Boot is broken for all DGS-1210 tested
devices as pressing RESET does not trigger it (only if pressed from a
running stock image)

UART pinout
-----------

[o]ooo|J14
 | ||`------ GND
 | |`------- RX
 | `-------- TX
 `---------- Vcc (3V3)

Installation using OEM upgrade
------------------------------

1. Make sure you are running OEM firmware in image2 slot (logged as admin):
   - > config firmware image_id 2 boot_up
   - > reboot
2. Install squashfs-factory_image1.bin to image1 using (logged as admin):
   - > download firmware_fromTFTP <tftpserver> factory_image1.bin
   - > config firmware image_id 1 boot_up
   - > reboot

Installation using serial interface
-----------------------------------

1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl839x-d-link_dgs-1210-52-initramfs-kernel.bin` command
5. Boot the image with `bootm` command

Once booted the initramfs, install the squashfs-sysupgrade.bin as a
normal OpenWrt system.

Dual-boot with stock firmware using writable u-boot-env
-------------------------------------------------------

From stock to OpenWrt / boot image 1 (CLI as admin):
   - > config firmware image_id 1 boot_up
   - > reboot

From OpenWrt to stock / boot image 2: (shell as root)
   - # fw_setenv bootcmd 'run addargs ; bootm 0xb4e80000'
   - # fw_setenv image '/dev/mtdblock7'
   - # reboot

Debrick using serial interface
------------------------------

1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should
   detect the switch
3. Flash the firmware.

Back to stock firmware using dual-boot
--------------------------------------

If you have serial interface, you can change u-boot env vars
interrupting the boot process. If not but you are running OpenWrt, you
can dual-boot (as mentioned eariler) and skip to step 4:

1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Boot the image 2:
   - set image /dev/mtdblock7; run addargs; bootm 0xb4e80000
4. Once booted, log as admin and change the boot image to 2
   - > config firmware image_id 2 boot_up
   - > reboot
5. After the boot, flash image1 with the vendor image

Back to stock firmware using DNA
--------------------------------

1. From an OpenWrt:
   - # fw_setenv bootstop on
   - # reboot
2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should
   detect the switch
3. Flash the firmware.

It has been developed and tested on device with F3 revision.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-09-17 21:28:21 +02:00
Markus Stockhausen
9ed1a1138e realtek: align DT macros in RTL839X with RTL838X
Add a missing definition to the RTL839X DT.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-17 21:28:21 +02:00
Markus Stockhausen
307e5cfc6e realtek: D-Link make common DT include generic
The D-Link DGS device tree was reorganized to better reflect the common
DT parts. The common include is named SOC specific (838X) and it seemed
like a good choice to add another common include in the future for the
RTL839X devices. From the current point of view this option is not really
needed.

1. The common part only includes data that matches RTL839X devices too.
2. The Panasonic DT structure avoids including the basic DTSI inside the
   common DTSI.

Taking simplicity of the Panasonic include logic and in perparation to
provide DGS-1210-52 support it makes sense to harmonize this.

- rename common include to reflect its content
- move the link to the root DTSI directly to the device specific DTS

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-17 21:28:21 +02:00
Olliver Schinagl
c4d030f24c
realtek: rtl838x: Fix ethernet polling timeout on probe
Due to an oversight we accidentally inverted the timeout check. This
patch corrects this.

Fixes: 9cec4a0ea4 ("realtek: Use built-in functionality for timeout loop")
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[ wrap poll_timeout line to 80 char ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2022-09-14 18:23:06 +02:00
Olliver Schinagl
9cec4a0ea4
realtek: Use built-in functionality for timeout loop
In commit 81e3017609 ("realtek: clean up rtl838x MDIO busy wait loop")
a hand-crafted loop was created, that nearly exactly replicate the
iopoll's `read_poll_timeout` functionality.

Use that instead.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-09-14 12:03:57 +02:00
Alexandru Gagniuc
01e2184c49 realtek: add support for TP-Link SG2210P
Add support for the TP-Link SG2210P switch. This is an RTL8380 based
switch with eight RJ-45 ports with 802.3af PoE, and two SFP ports.

This device shares the same board with the SG2008P and SG2008. To
model this, declare all the capabilities in the sg2xxx dtsi, and
disable unpopulated on the lower end models.

Specifications:
---------------
 - SoC:       Realtek RTL8380M
 - Flash:     32 MiB SPI flash (Vendor varies)
 - RAM:	      256 MiB (Vendor varies)
 - Ethernet:  8x 10/100/1000 Mbps with PoE (all ports)
              2x SFP ports
 - Buttons:   1x "Reset" button on front panel
 - Power:     53.5V DC barrel jack
 - UART:      1x serial header, unpopulated
 - PoE:       2x TI TPS23861 I2C PoE controller

Works:
------
  - (8) RJ-45 ethernet ports
  - (2) SFP ports (with caveats)
  - Switch functions
  - System LED

Not yet enabled:
----------------
  - Power-over-Ethernet (driver works, but doesn't enable "auto" mode)
  - PoE LEDs

Enabling SFP ports:
-------------------

The SFP port control lines are hardwired, except for tx-disable. These
lines are controller by the RTL8231 in shift register mode. There is
no driver support for this yet.

However, to enable the lasers on SFP1 and SFP2 respectively:

    echo 0x0510ff00 > /sys/kernel/debug/rtl838x/led/led_p_en_ctrl
    echo      0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.26
    echo      0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.24

Install via serial console/tftp:
--------------------------------

The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.

The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWrt:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U7)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as sson as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWrt.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[OpenWrt capitalisation in commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
ab2a4c1e01 realtek: rtl8380-tl-sg2xxx: use a single "firmware" partition
The "firmware" partition was assembled from two contiguous partitions.
This complexity is unnecessary. Instead of using mtd-concat over
"sys" and "usrimg1", simply declare the "firmware" partition to cover
the flash space instead.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
d55c087390 realtek: tl-sg2xxx: read MAC address from nvmem-cells
The TP-Link RTL83xx based switches have their MAC address programmed
in the "para" partition. While in theory, the format of this partition
is dynamic, in practice, the MAC address appears to be located at a
consistent address. Thus, use nvmem-cells to read this MAC address.

The main MAC is required for deriving the MAC address of the switch
ports. Instead of reading it via mtd_get_mac_binary(), alias the
ethernet0 node as the label-mac-device, and use get_mac_label().

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
5f026f1272 realtek: rtl838x: label switch port dts nodes
Although PHY nodes are labeled, the port nodes were not. Labeling of
ports is useful for 'status = "disabled"' ports, which is supported
since commit 9a7f17e11f ("realtek: ignore disabled switch ports")

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
bc9dcfb1ce realtek: split TP-Link SG2000 series devicetree
The TP-Link TL-SG2008, TL-SG2008P, and TL-SG2210P use the same board.
The main difference is that some footprints are not populated in the
lower-end models. To model this with minimal duplication, move the
devicetree to a common dtsi, leaving out just the board name.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[remove port relabelling from commit message, already merged with commit
 18a2b29aa1 ("realtek: tl-sg2008p: fix labeling of lan ports")]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-13 09:22:26 +02:00
Andreas Böhler
5f8c86e654 realtek: add support for TP-Link SG2452P v4 aka T1600G-52PS v4
This is an RTL8393-based switch with 802.3af on all 48 ports.

Specifications:
---------------
 * SoC:       Realtek RTL8393M
 * Flash:     32 MiB SPI flash
 * RAM:       256 MiB
 * Ethernet:  48x 10/100/1000 Mbps with PoE+
 * Buttons:   1x "Reset" button, 1x "Speed" button
 * UART:      1x serial header, unpopulated
 * PoE:       12x TI TPS23861 I2C PoE controller, 384W PoE budget
 * SFP:       4 SFP ports

Works:
------
  - (48) RJ-45 ethernet ports
  - Switch functions
  - Buttons
  - All LEDs on front panel except port LEDs
  - Fan monitoring and basic control

Not yet enabled:
----------------
  - PoE - ICs are not in AUTO mode, so the kernel driver is not usable
  - Port LEDs
  - SFP cages

Install via web interface:
-------------------------

Not supported at this time.

Install via serial console/tftp:
--------------------------------

The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U6)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as soon as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWRT.

Blind install via tftp:
-----------------------

This method works when it's not feasible to install a serial header.

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"
 3. Watch network traffic (tcpdump or wireshark works)
 4. Power on the device.
 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
 6. When 192.168.0.30 makes tftp requests, release pin 16
 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-09-10 22:13:52 +02:00
Bjørn Mork
2ca5602864 realtek: fix RTL839x receive tag decoding
The previous fixup was incomplete, and the offsets for the
queue and crc_error cpu_tag bitfields were still wrong on
RTL839x.

Fixes: 545c6113c9 ("realtek: fix RTL838x receive tag decoding")
Suggested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-09-09 22:11:55 +02:00
Bjørn Mork
545c6113c9 realtek: fix RTL838x receive tag decoding
Commit dc9cc0d3e2 ("realtek: add QoS and rate control") replaced a
16 bit reserved field in the RTL83xx packet header with the initial
cpu_tag word, shifting the real cpu_tag fields by one.  Adjusting for
this new shift was partially forgotten in the new RX tag decoders.

This caused the switch to block IGMP, effectively blocking IPv4
multicast.

The bug was partially fixed by commit 9d847244d9 ("realtek: fix
RTL839X receive tag decoding")

Fix on RTL838x too, including correct NIC_RX_REASON_SPECIAL_TRAP value.

Suggested-by: Jan Hoffmann <jan@3e8.eu>
Fixes: dc9cc0d3e2 ("realtek: add QoS and rate control")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-09-08 22:28:15 +02:00
Sander Vanheule
f1802b0db7 realtek: replace fix for spurious GPIO interrupts
8 and 16 bit writes to the GPIO peripheral are apparently not supported,
and only worked most of the time. This resulted in garbabe writes to the
interrupt mask registers, causing spurious unhandled interrupts, which
could lead to CPU lock-ups as these kept retriggering.

Instead of clearing these spurious interrupt when they occur, the
upstream patch will just make sure all register writes have the intended
result, so these don't happen at all.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-04 20:55:15 +02:00
Markus Stockhausen
78c0fb6927 realtek: Fix missing clock module CONFIG setting
Since introduction of clock driver we have a new kernel config
setting. Provide an initial value for the 930x targets.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-31 23:25:39 +02:00
Markus Stockhausen
6ff21c436d realtek: fix PLL register inconsistencies
Some devices have wrong/empty values in the PLL registers. Work
around that by reporting the default values.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-31 23:25:39 +02:00
John Audia
e0753c5d5c kernel: bump 5.10 to 5.10.139
All patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-08-31 23:25:39 +02:00
Alexandru Gagniuc
18a2b29aa1 realtek: tl-sg2008p: fix labeling of lan ports
The SG2008P has its ethernet ports in the rear, and LEDs in the front.
The ports should be labeled lan8->lan1, not lan1->lan8. To resolve
this, fix the phy mapping in the "ports" node.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-29 11:54:00 +02:00
Alexandru Gagniuc
f242f642bb realtek: tl-sg2008p: use correct i2c address for TPS23861
Address 0x30 is a "broadcast" address for the TPS23861. It should not
be used by drivers, as all TPS23861 devices on the bus are supposed to
respond. Change this to the correct address, 0x28.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-29 11:54:00 +02:00
Sander Vanheule
9a7f17e11f realtek: ignore disabled switch ports
When marking a switch port as disabled in the device tree, by using
'status = "disabled";', the switch driver fails on boot, causing a
restart:

    CPU 0 Unable to handle kernel paging request at virtual address
    00000000, epc == 802c3064, ra == 8022b4b4
        [ ... ]
    Call Trace:
    [<802c3064>] strlen+0x0/0x2c
    [<8022b4b4>] start_creating.part.0+0x78/0x194
    [<8022bd3c>] debugfs_create_dir+0x44/0x1c0
    [<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258
    [<80397508>] rtl838x_dbgfs_init+0xe0/0x56c

This is caused by the DSA subsystem (mostly) ignoring the port, while
rtl83xx_mdio_probe() still extracts some details on this disabled port
from the device tree, resulting in the usage of a NULL pointer where a
port name is expected.

By not probing ignoring disabled ports, no attempt is made to create a
debugfs directory later. The device then boots as expected without the
disabled port.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-29 08:32:42 +02:00
Markus Stockhausen
48f3746fe5 realtek: switch RTL838X/RTL839X DT to new clock driver
Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work
we need to change some nodes:
- define the external oscillator speed (25MHz)
- define SRAM
- add clock controller
- Add second CPU for RTL839X
- map all devices to new clocks
- Remove dummy LXB clock
- add CPU OPP table

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:48:30 +02:00
Markus Stockhausen
7c18aab6e0 realtek: activate clock driver for RTL838X/RTL839X targets
Make use the new clock driver for RTL838X and RTL839x target devices. Of course
we will enable their primary consumer (cpufreq-dt) too. To be careful just set
the default governor to userspace. As we rely on SRAM activate that module too.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:48:30 +02:00
Markus Stockhausen
5df36d4849 realtek: enable basic config for cpufreq framework
A new clock driver makes more sense if it can be used from consumers
like cpufreq.  Before we enable the driver we must tell the config that
the RTL838X and RTL839X targets allow CPU frequency changing.

Even though these targets currently rely on the CPU's internal R4K
timer, MIPS_EXTERNAL_TIMER is selected to allow for CPU frequency change
testing. The Realtek timers, which are clocked by the Lexra bus, still
need to be supported and used in order to provide correct wall times
when reclocking the CPU.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[add paragraph about MIPS_EXTERNAL_TIMER to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-28 11:45:03 +02:00
Markus Stockhausen
800d5fb3c6 realtek: add patch to enable new clock driver in kernel
Allow building the clock driver with kernel config options.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:31:21 +02:00
Markus Stockhausen
4850bd887c realtek: add RTL83XX clock driver
Add a new self-contained combined clock & platform driver that allows to
access the PLL hardware clocks of RTL83XX devices. Currently it provides
info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and
additionally allows to change the CPU clocks. Changing the clocks
multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and
is multithreading safe on the RTL839X. Even a cpufreq initiated change
of the CPU clock works fine. Loading the driver will add some meaningful
logging.

[0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz
[0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz,
           MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove trailing whitespaces, C-style SPDX comments for ASM and headers]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-28 11:30:58 +02:00
Markus Stockhausen
1efaad03bb realtek: add PLL DT binding includes
Add some constants for sharing between DT and drivers.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:03:34 +02:00
Markus Stockhausen
396e190f0b realtek: more generic platform initialization
Platform startup still "guesses" the CPU clock speed by DT fixed values.
If possible take clock rates from a to be developed driver and align to
MIPS generic platfom initialization code. Pack old behaviour into a
fallback function. We might get rid of that some day.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-20 11:49:30 +02:00