SFP cage of this device is connected via a AT8031 phy to port 5 of the switch.
This phy act as a RGMII-to-SerDes converter.
Also a I2C clock gate needs to be enabled in order to access the SFP module via I2C bus.
SFP cage also has module detect pin which is connected to I2C gpio expander.
With this patch the kernel/PHYLINK now can detect, readout and use the SFP module/port.
NOTE: SFP cage / AT8033 PHY only support 1000base-X encoding!
This means that some SGMII modules can work and only at forced 1GBit/full-duplex!
Signed-off-by: René van Dorst <opensource@vdorst.com>
These stock partitons: "backup", "hw_panic", "overly", firmware_backup", "opt"
do not contain any device-specific data and can be used for /overlay, resulting in
121M space
Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
