In target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c,
make rtl838x_pie_rule_write() return non-zero value case of error.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Make sure functions calling rtl838x_smi_wait_op() return its return
value in target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c.
This brings the code style in line with the rtl839x implementation.
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
A behavioural change was introduced with commit 758c88b969 ("realtek:
Whitespace and codestyle cleanup") causing rtl838x_read_phy() and
rtl838x_write_phy() to unconditionally return -ETIMEDOUT. As a result,
probing the device during boot fails:
Error setting up netdev, freeing it again.
rtl838x-eth: probe of 1b00a300.ethernet failed with error -5
Fix the bootloop caused by this regression with kernel 5.15 on rtl838x
devices, by properly returning 0 on success.
Tested on a Netgear GS108T v3, a Netgear GS310TP v1, a Zyxel GS1900-8HP
v1 and an HPE 1920-8G.
Fixes: 758c88b969 ("realtek: Whitespace and codestyle cleanup")
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Upstream generic MIPS uses 0x80100000 and 0x80100400 for the LOADADDR
and ENTRY addresses. As we do not want to diverge from upstream and
patch upstream when not needed, adjust our addresses as well to be
future proof.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
ZyXEL GS1900 devices with SoCs from both the RTL838x and RTL839x
families share the same image structure and size of the firmware
partition. Additionally, the GS1900-48 recipe provided a parameter for
the zyxel-vers command, but this parameter is not used. Deduplicate the
recipes by moving it to target/linux/realtek/image/common.mk.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The listed partition size doesn't match the original partition size, and
actually overlaps with the following partition. The partition node name
for the "firmware" partition also has an extra 'b' compared to the
partition offset.
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900-48 firmware image is identified by the 'AAHN' ID, while the
GS1900-48HP is identified by 'AAHO' [1]. The latter was used, resulting
in the following error message when upgrading via the stock web UI:
Device only can support firmware from V1.00(AAHN.0) and later version
Fix image generation by using the correct ID.
[1] https://download.zyxel.com/GS1900-48/firmware/GS1900-48_2.70(AAHN.3)C0_2.pdf
Link: https://forum.openwrt.org/t/146533
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Suggested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
While cleaning up the makefiles for the realtek target, the order of the
default image generating commands was accidentally changed. This caused
the image signature to end up somewhere in the middle, misaligning the
rootfs. As a result, sysupgrade couldn't verify upgrade images anymore,
and devices end up in a boot loop due to the unaligned (and not found)
rootfs.
Fixes: 94d8b4852b ("realtek: Cleanup Makefiles")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The reset register on RTL93xx not merely have bits to execute
a reset of a hardware component, but also configuration bits for
reset procedures. Keep them during executing a reset.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[backport to 5.10 kernel]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Linus prefers to have loop initializers nice and tightly scoped. In
OpenWRT this has been possible since 41a1a652fb ("kernel: backport
gnu11 upgrade").
This patch cleans up variable scope while trying to do the above for
'simple for loops'.
This cleans up and simplifies some functions and code, and pulls in
variables to a smaller scope.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Our current Makefiles a little bit messy and can be improved somewhat,
both in whitespace and in style.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
The only exception to C++ style comments are SPDX license identifier
markers at the start of C files (even headers have C style markers).
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Fix some ugly whitepsaces and codestyle issues around the realtek sources.
While this is by no means perfect, it catches what it caught.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
A full loop accessing all FDB entries can take several milliseconds
(on RTL839x about 20 ms), so give other kernel tasks a chance to run.
This is especially important for rtl83xx_port_fdb_dump which is itself
called in a loop for all ports by the kernel.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
These two functions are identical apart from writing different values to
the read/write bit. Create a new function rtl_table_exec to reduce code
duplication.
Also replace the unbounded busy-waiting loop. The new implementation may
sleep, but as the hardware typically responds before the first poll, any
callers doing many table accesses still need to make sure not to block
other kernel tasks themselves.
So far, polling timeout errors are only handled by logging an error, but
a return value is added to allow proper handling in the future.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
This function currently prints three messages for every switch port at
KERN_INFO level. This takes a considerable amount of time during bootup
and can even trigger an external watchdog.
Replace these log messages by a single one at KERN_DEBUG level.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
As learning for the CPU port is now disabled globally, the bit in the
TX header doesn't have any effect anymore. Remove it to make the header
consistent with the global configuration.
Originally, this change was intended to be applied before commit
eb456aedfe ("realtek: use assisted learning on CPU port"), which is
why the commit message incorrectly mentions that the TX header already
disables learning.
The reason for disabling learning on the CPU port in the first place is
that it doesn't work correctly when packets are trapped to the CPU and
then forwarded by the CPU to other ports. In that case, the switch would
incorrectly learn the CPU port as source. An example that triggered this
issue are Multicast Listener Reports and IGMP membership reports.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
- rtl83xx_vlan_filtering()
"struct switchdev_trans *trans" parameter was removed[1] and
"struct netlink_ext_ack *extack" was added[2].
[1]: https://www.spinics.net/lists/netdev/msg712250.html
[2]: https://www.spinics.net/lists/netdev/msg722496.html
- rtl83xx_vlan_add/del()
vlan->vid_begin and vlan->vid_end were removed and vlan->vid was
added[3].
[3]: https://www.spinics.net/lists/netdev/msg712248.html
- rtl83xx_vlan_prepare()
"port_vlan_prepare" member was removed from "dsa_switch_ops" struct
in dsa.h[4] and vlan_prepare function should be called from vlan_add
function. Also, change return type of vlan_add function to int.
[4]: https://www.spinics.net/lists/netdev/msg712252.html
- rtl83xx_port_mdb_add()
"port_mdb_prepare" member in "dsa_switch_ops" struct was removed and
preparation need to be done in the function of "port_mdb_add" member
instead. And also, int type need to be returned on "port_mdb_add"
member[5].
[5]: https://www.spinics.net/lists/netdev/msg712251.html
- rtl83xx_port_pre_bridge_flags(), rtl83xx_port_bridge_flags()
The current "port_pre_bridge_flags" member and "port_bridge_flags"
member in "dsa_switch_ops" in dsa.h has flags of
"struct switchdev_brport_flags" type instead[6], so adjust to it.
And, the changed features are passed by flags.mask[7] in
rtl83xx_port_bridge_flags(), so check it before calling function
to enable/disable fieature.
[6]: https://lore.kernel.org/lkml/20210212151600.3357121-7-olteanv@gmail.com/
[7]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e18f4c18ab5b0dd47caaf8377c2e36d66f632a8c
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[shorten final return statement of rtl83xx_port_mdb_add()]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
- 007-5.16-gpio-realtek...: upstreamed on 5.16 and backported to 5.15.3
- 708-brflood-spi.patch : upstreamed
- 709-lag-offloading.patch: upstreamed
- 713-v5.12-net-dsa-... : upstreamed and some implementations are
replaced
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The following drivers were upstreamed and available on 5.15, so drop
from OpenWrt tree.
- realtek-otto-gpio (5.13)
- realtek-rtl-spi (5.12)
- realtek-rtl-intc (5.12)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
add three missing LEDs
- PoE-Max
- Link/Act
- PoE
add two missing buttons
- mode
- reset
The last was dropped in
commit 61a3d0075b ("realtek: update GPIO bindings in the dts files in dts-5.10")
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
General hardware info:
----------------------
D-Link DGS-1210-28MP rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC @ 500MHz,
DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 370W.
Power over Ethernet:
--------------------
The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU.
In order to enable PoE, the realtek-poe package is required. It is
installed by default, but currently it requires the manual editing of
/etc/config/poe. Keep in mind that the port number assignment does not
match on this switch, alway 8 ports are in reversed order: 8-1, 16-9 and
24-17.
LEDs and Buttons:
-----------------
On stock firmware, the mode button is supposed to switch the LED indicators
of all port LEDs between Link Activity and PoE status. The currently
selected mode is visualized using the respective LEDs. PoE Max indicates
that the maximum PoE budget has been reached.
Since there is currently no support for this behavior, these LEDs and
the mode button can be used independently.
Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.
Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
OEM installation from Web Interface:
------------------------------------
1. Make sure you are booting using OEM in image 2 slot. If not, switch to
image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image in vendor firmware via Tools > Backup / Upgrade
Firmware > image1
3. Toogle startup image via System > Firmware Information > Boot from
image1
4. Tools > reboot
Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:
Boot initramfs image from U-Boot:
---------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000
openwrt-rtl838x-generic-d-link_dgs-1210-28mp-f-initramfs-kernel.bin`
command
5. Boot the image with `bootm` command
Signed-off-by: Andreas Böhler <dev@aboehler.at>
should be add/delete or abbreviated add/del
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
The code in dsa.c:rtl83xx_port_enable() was trying to set
vlan_port_tag_sts_ctrl while dealing with differences between SoCs.
However, not only that register has a different address, the register
structure and even the 2-bit value semantic changes for each SoC.
The vlan_port_tag_sts_ctrl field was dropped and converted into a
vlan_port_keep_incoming_tag_set() function that abstracts the different
between SoCs. The macro referencing that register migrated to the SoC
specific c file as it will be privately used by each file.
All magic numbers were converted into macros using BITMASK and
FIELD_PREP.
The vlan_port_tag_sts_ctrl debugfs was dropped for now as it is already
broken for rtl93xx. The best place for SoC specific code might be in each
respective c file and not in if/else clauses.
The final result is:
rtl838x: set ITAG_STS=TAGGED, same as before
rtl839x: set ITAG_STS=TAGGED instead of IGR_P_ITAG_KEEP=0x1, fixing
forwarding of tagged packets
rtl930x: set EGR_ITAG_STS=TAGGED instead of IGR_P_ITAG=0x1, possibly
fixing forwarding of tagged packets
rtl931x: set EGR_ITAG_STS=TAGGED instead of OTPID_KEEP=0x1, possibly
fixing forwarding of tagged packets
Without (EGR_)ITAG_STS=TAGGED, at least for rtl839x, forwarded packets
will drop the vlan tag while packets from the CPU will still have the
correct tag.
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
The rtl930x speed status registers require 4 bits to indicate the speed
status. As such, we want to divide by 8. To make things consistent with
the rest of this code, use a bitshift however.
This bug probably won't affect many users yet, as there aren't many
rtl930x switches in the wild yet with more then 10 ports, and thus a
low-impact bugfix.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[also fix port field extraction]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
After replacing the R4K event timer and clock source with the new
Realtek Otto timer, performance for RTL839x devices was severely
impacted, as reported by Hiroshi.
Research by Markus showed that after commit 4657a5301e ("realtek:
avoid busy waiting for RTL839x PHY read/write"), the ethernet driver
could only update a phy once per timer interval, which also heavily
impacted boot time. On e.g. a Zyxel GS1900-48, this added around a
minute to the time to fully initialise the switch.
By marking the otto clocksource as continuous, the kernel enables it to
be used for high resolution timers. This allows readx_poll_timeout() to
sleep for less than one system timer interval, reducing system dead
time.
Link: https://github.com/openwrt/openwrt/issues/11117
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Cc: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
In rtl83xx_set_features we set bit 3 to enable, and bit 4 to disable
checksuming. Looking at rtl93xx_set_features we however see that for
both enable and disable the same bit is used (bit 4). This can't be
right, especially as bit 4 for rtl83xx seems to be Collision threshold
occupying 2 bits. Change this to make this more logical.
Fixes: 9e8d62e421 ("realtek: enable CRC offloading")
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
L2 learning on the CPU port is currently not consistently configured and
relies on the default configuration of the device. On RTL83xx, it is
disabled for packets transmitted with a TX header, as hardware learning
corrupts the forwarding table otherwise. As a result, unneeded flooding
of traffic for the CPU port can already happen on some devices now. It
is also likely that similar issues exist on RTL93xx, which doesn't have
a field to disable learning in the TX header.
To address this, disable hardware learning for the CPU port globally on
all devices. Instead, enable assisted learning to let DSA write FDB
entries to the switch.
For now, this does not sync local/bridge entries to the switch. However,
support for that was added in Linux 5.14, so the next switch to a newer
kernel version is going to fix this.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Initialize the data structure using memset to avoid the possibility of
writing garbage values to the hardware.
Always set a valid entry type, which should fix writing unicast entries
on RTL930x.
For unicast entries, set the is_static flag to prevent the switch from
aging them out.
Also set the rvid field for unicast entries. This is not strictly
necessary, as the switch fills it in automatically from a non-zero vid.
However, this makes the code consistent with multicast entry setup.
While at it, reorder the statements and fix some style issues (double
space, comma instead of semicolon at end of statement). Also remove the
unneeded priv parameter and debug print for the multicast entry setup
function.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The switches support different actions for incoming ethernet multicast
frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The
current code will set the 2-bit action field to FLOOD (0x3) for most
classes, but the highest bit is always unset for the relevant control
registers. This means the DROP (0x1) action being used for these
classes; whatever class the MSB happens to be in.
For RTL838x, this results in {20,23-2F} frames being dropped, instead of
flooding all ports. On other switch generations, {0F,1F,2F} frames are
dropped. This is inconsistent, and appears to be a mistake. Remove this
inconsistency by flooding all multicast frames with RMA addresses.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The multicast setup function rtl838x_eth_set_multicast_list() checks if
the current SoC is a RTL839x family device. However, the function is
only included in the RTL838x ops table, so this path should never be
taken, making this dead code. rtl839x_eth_set_multicast_list() is
already present in the RTL839x ops table, so it should be safe to remove
this branch.
While touching the code, also re-sort the functions to match sorting
elsewhere, with rtl838x coming before rtl839x.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Currently several messages at KERN_INFO level are printed for every FDB
del/dump operation. This can cause a significant slowdown for example
while using "bridge fdb", and may even trigger a watchdog.
Remove most of these log messages, as the new L2 table debugfs node
should be a good replacement. Change the remaining messages to
KERN_DEBUG level.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Switch to a polling implementation similar to the one for RTL838x, to
allow other kernel tasks to run while waiting.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The new timer is not yet ready for all targets. Avoid interactive
questions during build
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[rename symbol to CONFIG_REALTEK_OTTO_TIMER]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the new timer driver for the RTL839X devices and remove the
no longer needed modules.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
