The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.
Where the majority of devices is using it, also move the serial0
alias to the DTSI.
*) Since GL-USB150 even defines serial0 alias, the missing uart
is probably just a mistake. Anyway, disable it for now so this
patch stays cosmetic.
Apply this to 21.02 as well to remove an unnecessary backporting
pitfall.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 3a4b751110)
ath79.dtsi uses ATH79_CLK_MDIO, so the include
<dt-bindings/clock/ath79-clk.h>
needs to be moved there.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
The QCA9550 family of SoCs have a slightly different reset
sequence compared to older chips.
Normally the bootloader performs this sequence, however
some bootloader implementation expect the operating system
to clear the reset. Also get the PCIe resets from OF to
support the second RC of the QCA9558.
This is required for the AVM FRITZ!WLAN Repeater 1750E to work,
as EVA leaves the PCIe bus in reset.
Tested: AVM FRITZ!WLAN Repeater 1750E - OCEDO Koala
Signed-off-by: David Bauer <mail@david-bauer.net>
Currently AR724x pinmux for register 0x18040028 controls only JTAG disable bit.
This patch adds new DTS settings to control LAN LEDs and CLKs that allow
full software control over these diodes - exactly the same is done by ar71xx
target in device setup phase for many routers (WNR2000v3 for example).
'switch_led_disable_pins' clears AR724X_GPIO_FUNC_ETH_SWITCH_LED[0-4]_EN bits.
'clks_disable_pins' clears AR724X_GPIO_FUNC_CLK_OBS[1-5]_EN and
AR724X_GPIO_FUNC_GE0_MII_CLK_EN bits. These all should be used together, along
with 'jtag_disable_pins', to allow OS to control all GPIO-connected LEDs and
buttons on device.
Signed-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>
Add the syscon compatible, otherwise used functions like
syscon_regmap_lookup_by_phandle() will return an error and setting the
ethernet pll data wont work at all.
Fix the pll register width. Writing to registers out of the range via
syscon isn't possible and returns an error. On ar7242 the last pll
register - Current Audio Modulation Logic Output - is at 0x1805003c.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Some maintainers prefer DTS files licensed under permissive license like
MIT / BSD. As all DT bindings should be OS independent and DTS files are
pretty separated from Linux code it probably makes sense to share them
across projects.
The safest solution is to use dual licensing: that way it stays clear
these files can be used in GPL projects without depending on current
belief of licenses compatibility.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: John Crispin <john@phrozen.org>
This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.
Signed-off-by: John Crispin <john@phrozen.org>
