The ath10k driver will load both pre-calibration data and board-2.bin
if board-2.bin exists. So it's not necessary to remove it. And this
change won't increase jffs2 image size.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Backport at803x split patches merged upstream to tidy things up for the
at803x PHY driver.
New Kernel config are introduced hence any user needs to be updated.
Downstream ipq40xx patch require rework to correctly move them to the
qcom specific PHY directory.
All affected patch automatically refreshed.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Only bcm2708 and bcm2709 use "kernel.img" file name.
bcm2710 and bcm2711 use "kernel8.img" and bcm2712 uses "kernel_2712.img".
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Automatically detect boot partition instead of forcing /dev/mmcblk0p1.
This way users can still get /boot mounted when booting from USB.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Add missing Rasoberry Pi 5 board_name to set_preinit_iface in order to get
ethernet working on failsafe mode.
Fixes: 8b63d9a ("bcm27xx: add new bcm2712 subtarget")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
* fix switch ports with modes other than 1000M/Full
* set 32-bit dma_coherent_mask to get PPE to work with 4 GiB of RAM
* sync driver for built-in 1GE PHY with MediaTek SDK sources
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The qca8081 phy needs to set the reset delay time,
otherwise it will not be detected by the mdio bus.
Fixes: 75ad5c2 ("qualcommax: switch to qca8081 upstream PHY driver")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Switch to qca8081 upstream PHY. Update every device that have LEDs
attached to the qca8081 PHY to follow new way of defining the LEDs and
add original OEM configuration.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport upstream patch adding more speed modes to LED netdev trigger.
Fixes: 2c39269b6e ("generic: 6.1: backport qca808x LED support patch")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport qca808x LED support patch merged upstream needed to drop
handling of it from the SSDK for ipq807x target.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport merged upstream patch that adds support for firmware loader
from NVMEM or attached filesystem for Aquantia PHYs.
Refresh all kernel patches affected by this change.
Also update the path for aquantia .ko that got moved to dedicated
directory upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
[rmilecki: port to 5.15]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
They are unnecessary since ipq806x switched to DSA in
the commit 337e36e0ef.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Refresh HSGMII patch due to recent PHY backport that cause
compilation warning for case not handled in phy_interface_num_ports.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Refresh 2.5G-SGMII patch due to recent PHY backport that cause
compilation warning for case not handled in phy_interface_num_ports.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
In order to get rid of having to modify U-boot bootcmd and having U-boot
load the Aquantia PHY-s firmware lets use some of the free space on SPI-NOR
to add a second ethphyfw partition and be able to load AQR FW via NVMEM
cells.
Signed-off-by: Robert Marko <robimarko@gmail.com>
It seems that the reset GPIO-s defined for the two AQR PHY-s are actually
reversed.
Manually testing confirmed that GPIO44 is actually reset GPIO of AQR at 0,
while GPIO59 is reset of AQR at 8:
root@OpenWrt:~# mdio 9*
DEV PHY-ID LINK
0x00 0x00000000 down
0x08 0x00000000 down
0x10 0x004dd0b1 down
0x11 0x004dd0b1 down
0x12 0x004dd0b1 down
0x13 0x004dd0b1 up
0x14 0x004dd0b1 down
0x15 0x04820a05 down
root@OpenWrt:~# gpioset gpiochip0 44=0
root@OpenWrt:~# mdio 9*
DEV PHY-ID LINK
0x08 0x00000000 down
0x10 0x004dd0b1 down
0x11 0x004dd0b1 down
0x12 0x004dd0b1 down
0x13 0x004dd0b1 up
0x14 0x004dd0b1 down
0x15 0x04820a05 down
root@OpenWrt:~# gpioset gpiochip0 44=1
root@OpenWrt:~# mdio 9*
DEV PHY-ID LINK
0x00 0x00000000 down
0x08 0x00000000 down
0x10 0x004dd0b1 down
0x11 0x004dd0b1 down
0x12 0x004dd0b1 down
0x13 0x004dd0b1 up
0x14 0x004dd0b1 down
0x15 0x04820a05 down
root@OpenWrt:~# gpioset gpiochip0 59=0
root@OpenWrt:~# mdio 9*
DEV PHY-ID LINK
0x00 0x00000000 down
0x10 0x004dd0b1 down
0x11 0x004dd0b1 down
0x12 0x004dd0b1 down
0x13 0x004dd0b1 up
0x14 0x004dd0b1 down
0x15 0x04820a05 down
root@OpenWrt:~# gpioset gpiochip0 59=1
root@OpenWrt:~# mdio 9*
DEV PHY-ID LINK
0x00 0x00000000 down
0x08 0x00000000 down
0x10 0x004dd0b1 down
0x11 0x004dd0b1 down
0x12 0x004dd0b1 down
0x13 0x004dd0b1 up
0x14 0x004dd0b1 down
0x15 0x04820a05 down
Signed-off-by: Robert Marko <robimarko@gmail.com>
Now that we have support for firmware loading via the kernel driver, it
makes sense to populate the firmware name as well, so if its present the
driver can load it.
In later patches, loading the FW via NVMEM will be added as well.
Signed-off-by: Robert Marko <robimarko@gmail.com>
This patch adds support for Raspberry Pi 5.
Instead of using 16K pages like Raspberry Pi OS, OpenWrt uses 4K pages due to
incompatibilities with F2FS and other applications.
There are multiple RPi forum posts with different cases and users are forcing
kernel8.img to workaround them, which is the 64 bit kernel of the RPi 4.
However, this isn't possible in OpenWrt because we only ship one kernel and we
would have to add RPi 5 support to bcm2711 subtarget (RPi 4) for that
workaround to work in OpenWrt.
Specification:
- Processor Broadcom BCM2712 2.4GHz quad-core 64-bit Arm Cortex-A76 CPU,
with cryptographic extension, 512KB L2 caches per core, 2048KB L3 cache
Features:
- VideoCore VII GPU, supports OpenGL ES 3.1, Vulkan 1.2
- Dual 4Kp60 HDMI display output with HDR support 4Kp60 HEVC decoder
- LPDDR4X-4267 SDRAM 4GB and 8GB
- Dual-band 802.11ac Wi-Fi
- Bluetooth 5.0 / Bluetooth Low Energy
- microSD card slot, with support for SDR104 high-speed mode
- 2 x USB 3.0 ports
- 2 x USB 2.0 ports
- Gigabit Ethernet
- 2 x 4 lane MIPI camera/display
- PCIe 2.0 x1
- 5V/5A power via USB-C
- Raspberry Pi standard 40-pin header
- Real-time clock RTC
- Power button
Build system: x86_64
Build-tested: bcm2712
Run-tested: bcm2712/RPi5
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[Remove device variant, improve description]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Add support for BCM2712 (Raspberry Pi 5).
3bb5880ab3
Patches were generated from the diff between linux kernel branch linux-6.1.y
and rpi-6.1.y from raspberry pi kernel source:
- git format-patch linux-6.1.y...rpi-6.1.y
Build system: x86_64
Build-tested: bcm2708, bcm2709, bcm2710, bcm2711
Run-tested: bcm2710/RPi3B, bcm2711/RPi4B
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[Remove applied and reverted patches, squash patches and config commits]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Ubiquiti Rocket M XW is a single-band, 2x2:2 external Wi-Fi AP, with optional
GPS receiver, with two external RP-SMA antenna connections, based on
AR9342 SoC. Two band variants exists, for 2.4GHz and 5GHz band, usable
with the same image.
Specs:
- CPU: Atheros AR9342 MIPS SoC at 535MHz
- RAM: 64MB DDR400
- ROM: 8MB SPI-NOR in SO16W package, MX25L6408E
- Wi-Fi Atheros AR9342 built-in 2x2:2 radio
- Ethernet: Atheros AR8035 PHY, limited to 100Mbps speeds due to
magnetics
- Power: 24V passive PoE input.
Installation: please refer to Ubiquiti Bullet M2HP for documentation.
The device runs with exactly same image as the Bullet, and after fixes
in preceding commit, is fully functional again. Add the alternative name
to the build system.
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Since commit 6f2e1b7485 ("ath79: disable delays on AT803X config init")
Ubiquiti XW boards equipped with AR8035 PHY suffered from lack of
outbound traffic on the Ethernet port. This was caused by the fact, the
U-boot has set this during boot and it wasn't reset by the PHY driver,
and the corresponding setting in device tree was wrong.
Set the 'phy-mode = "rgmii-txid"' at the ð0, and drop this property
from PHY node, as it is not parsed there. This causes the device to
connect using Ethernet once again.
Fixes: db4b6535f8 ("ath79: Add support for Ubiquity Bullet M (XW)")
Fixes: 6f2e1b7485 ("ath79: disable delays on AT803X config init")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Onboard AR8035 PHY supports 1000Base-T operation, but onboard
Ethernet magnetics do not. Reduce advertised link speeds to 100Mbps and
lower.
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Add support for loading Aquantia FW from NVMEM for Zyxel NBG7815
restoring correct functionality of the 10g port.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add pending patch for ipq4019 MDIO MDC rate fix. The divisor was never
actually set resulting in the MDC rate running at a very low speed.
The same MDIO is used on ipq807x where Aquantia PHY are commonly used
where MDIO is used to load the PHY firmware. Running at higher speed is
required to make the firmware load faster as it does reduce load time
from 60+ second to 5-6 seconds.
Add as pending as upstream there seems to be some conflicts with quic
and me and it might take lots of time before this is effectively merged
upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The safe max frame size for this ethernet switch is 1532 bytes,
excluding the DSA TAG and extra VLAN header, so the maximum
outgoing frame is 1542 bytes.
The available overhead is needed when using the DSA switch with
a cascaded Marvell DSA switch, which is something that exist in
real products, in this case the Inteno XG6846.
Use defines at the top of the size for max MTU so it is clear how
we think about this, add comments.
We need to adjust the RX buffer size to fit the new max frame size,
which is 1542 when the DSA tag (6 bytes) and VLAN header (4 extra
bytes) is added.
We also drop this default MTU:
#define ENETSW_TAG_SIZE (6 + VLAN_HLEN)
ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
in favor of just:
ndev->mtu = ETH_DATA_LEN;
I don't know why the default MTU is trying to second guess the
overhead required by DSA and VLAN but the framework will also
try to bump the MTU for e.g. DSA tags, and the VLAN overhead is
not supposed to be included in the MTU, so this is clearly not
right.
Before this patch (on the lan1 DSA port in this case):
dsa_slave_change_mtu: master->max_mtu = 9724, dev->max_mtu = 10218, DSA overhead = 8
dsa_slave_change_mtu: master = extsw, dev = lan1
dsa_slave_change_mtu: master->max_mtu = 1510, dev->max_mtu = 9724, DSA overhead = 6
dsa_slave_change_mtu: master = eth0, dev = extsw
dsa_slave_change_mtu new_master_mtu 1514 > mtu_limit 1510
mdio_mux-0.1:00: nonfatal error -34 setting MTU to 1500 on port 0
My added debug prints before the nonfatal error: the first switch from the top
is the Marvell switch, the second in the bcm6368-enetsw with its 1510 limit.
After this patch the error is gone.
OpenWrt adds a VLAN to each port so we get VLAN tags on all frames. On this
setup we even have 4 more bytes left after the two DSA tags and VLAN so
we can go all the way up to 1532 as MTU.
Testing the new 1532 MTU:
eth0 ext1 enp7s0
.--------. .-----------. cable .------.
| enetsw | <-> | mv88e6152 | <-----> | host |
`--------´ `-----------´ `------´
On the router we set the max MTU for test:
ifconfig eth0 mtu 1520
ifconfig br-wan mtu 1520
ifconfig ext1 mtu 1506
An MTU of 1506 on ext1 is a logic consequence of the above setup:
this is the max bytes actually transferred. The framing added will be:
- 18 bytes standard ethernet header
- 4 bytes VLAN header
- 6 bytes DSA tag for enetsw
- 8 bytes DSA tag for mv88e6152
Sum: 1506 + 18 + 4 + 6 + 8 = 1542 which is out max frame size.
Test pinging from host:
ping -s 1478 -M do 192.168.1.220
PING 192.168.1.220 (192.168.1.220) 1478(1506) bytes of data.
1486 bytes from 192.168.1.220: icmp_seq=1 ttl=64 time=0.696 ms
1486 bytes from 192.168.1.220: icmp_seq=2 ttl=64 time=0.615 ms
Test pinging from router:
PING 192.168.1.2 (192.168.1.2): 1478 data bytes
1486 bytes from 192.168.1.2: seq=0 ttl=64 time=0.931 ms
1486 bytes from 192.168.1.2: seq=1 ttl=64 time=0.810 ms
The max IP packet without headers is 1478, the outgoing ICMP packet is
1506 bytes. Then the DSA, VLAN and ethernet overhead is added.
Let us verify the contents of the resulting ethernet frame of 1542 bytes.
Ping packet on router side as viewed with tcpdump:
00:54:51.900869 AF Unknown (1429722180), length 1538:
0x0000: 3d93 bcae c56b a83d 8874 0300 0004 8100 =....k.=.t......
0x0010: 0000 dada 0000 c020 0fff 0800 4500 05e2 ............E...
0x0020: 0000 4000 4001 b0ec c0a8 0102 c0a8 01dc ..@.@...........
0x0030: 0800 7628 00c3 0001 f5da 1d65 0000 0000 ..v(.......e....
0x0040: ce65 0a00 0000 0000 1011 1213 1415 1617 .e..............
0x0050: 1819 1a1b 1c1d 1e1f 2021 2223 2425 2627 .........!"#$%&'
0x0060: 2829 2a2b 2c2d 2e2f 3031 3233 3435 3637 ()*+,-./0123456
(...)
- 3d93 = First four bytes are the last two bytes of the destination
ethernet address I don't know why the first four are missing,
but it sure explains why the paket is 1538 bytes and not 1542
which is the actual max frame size.
- bcae c56b a83b = source ethernet address
- 8874 0300 0004 = Broadcom enetsw DSA tag
- 8100 0000 = VLAN 802.1Q header
- dada 0000 c020 0fff = EDSA tag for the Marvell (outer) switch,
- 0800 is the ethertype (part of the EDSA tag technically)
- Next follows the contents of the ping packet as it appears if
we dump it on the DSA interface such as tcpdump -i lan1
etc, there we get the stripped out packet, 1506 bytes.
- At the end 4 bytes of FCS.
This clearly illustrates that the DSA tag is included in the MTU
which we set up in Linux, but the VLAN tag and ethernet headers and
checksum is not.
Tested-by: Paul Donald <newtwen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
This reverts commit dcdcfc1511.
This is a firmware for third-party u-boot mod, which should not
be carried here by us.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
The current dts file of dgs-1210-10p doesn't support link states
for the sfp ports (they are always up).
This patch tries to give better support for this and was run tested
on dgs-1210-10p.
It was heavily inspired from Paul Fertser, RaylynnKnight
and the author of dgs-1210-10mp-f.dts
https://forum.openwrt.org/t/dlink-dgs-1210-10p-with-glc-t-co-sfp/170928
Signed-off-by: Michel Thill <jmthill@gmail.com>
Commit e816591e22 ("ath79: qca: convert to nvmem-layout") mistakenly
switched the source of the mac address from the 'info' to 'art'
partition.
This patch updates all devices that share same 'parent' device tree file
and was tested to fix the problem for eap225-outdoor-v3 - device that I
actually own.
Fixes: e816591e22 ("ath79: qca: convert to nvmem-layout")
Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enabling SMP on Danube[1] is incompatible with a patch that
adds support for interrupt handling on all cores on other
platforms[2]. This patch fixes the mentioned issue.
1. 084c20f6c5 ("lantiq: xway: kernel: enable SMP support ")
2. fbd33d6164 ("lantiq: enable interrupts on second VPEs")
Fixes: #13934Fixes: #14283
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
By default Linux will default to most IRQ-s being mapped to core 0 which
during high loads will completely swamp the core 0, so lets add the widely
used script that has been floating around forums for a long time to try and
optimize the IRQ mapping a bit.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some of devices in this target have only 8 MiB space and are closing to
borders of usable space. Particularly, TP-Link RE305 v1 already suffers
from this issue[1], where with current partition layout, on release
images, there's not enough space for overlay. So activate small_flash
feature, which will remove some userspace hardening but will gain almost
1 MiB additional flash memory space. Here is small size comparison of
similar device (RE365 v1) with default config + LuCI:
kernel rootfs sysupgrade
current: 2305728 3635044 5964584
small_flash: 1713571 3320132 5047080
1. https://github.com/openwrt/openwrt/issues/14215
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Renumber backport patches starting from 000 to tidy things up.
Also fix patch name format for the mmc backport patch.
Refresh patches affected by this renumber change.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Move stmmac backport fix patches from ipq806x to generic backport
directory as they got merged upstream and they fix wide performance
regression.
This will eventually cause performance increase on any user of the
stmmac driver.
Generic patch automatically refreshed with make target/linux/refresh.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support for Ubiquiti LiteBeam M5 (XW).
The device was previously supported in ar71xx.
See commit: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commit;h=d0988235dd277b9a832bbc4b2a100ac6e821f577
Add ALTX_MODEL for Ubiquiti AirGrid M5 HP (XW), Ubiquiti PowerBeam M5 300 (XW) in generic-ubnt.mk
This models are identical (firmware-wise) to the already supported Ubiquiti Nanostation Loco M (XW)
Add also Ubiquiti NanoBeam M5 to ALTX_MODEL of Ubiquiti Nanostation Loco M (XW) since it's another clone.
Tested on:
- Ubiquiti LiteBeam M5 (XW)
- Ubiquiti PowerBeam M5 (XW)
This also modify target/ath79/dts/ar9342_ubnt_xw.dtsi to use nvmem for calibration data
Checked that the caldata size in the eeprom partition are actually 0x440 on:
- Ubiquiti PowerBeam M5 (XW)
- Ubiquiti Nanostation M5 (XW)
- Ubiquiti LiteBeam M5 (XW)
- Ubiquiti AirGrid M5 HP (XW)
Signed-off-by: Samuele Longhi <agave@dracaena.it>
Booting from non-MMC devices on Rockchip targets without this
change results in a boot failure:
Model: FriendlyElec NanoPi R5S
Net: eth0: ethernet@fe2a0000
Hit any key to stop autoboot: 0
** Booting bootflow 'nvme#0.blk#1.bootdev.part_1' with script
** No partition table - mmc 0 **
** No partition table - mmc 0 **
Couldn't find partition mmc 0:1
Can't set block device
Wrong Image Type for bootm command
ERROR -91: Protocol wrong type for socket: can't get kernel image!
Boot failed (err=1)
This change fixes the default boot script for Rockchip targets to
support booting from non-MMC devices such as NVMe or USB drives.
Some targets with only a boot rom (e.g. NanoPi R5S) may require u-boot
to be installed on the eMMC or a MicroSD card in order to boot from
non-MMC devices.
Fixes: #14420
Reviewed-by: Tianling Shen <cnsztl@immortalwrt.org>
Signed-off-by: Justin Klaassen <justin@tidylabs.app>
The WLAN + WED reset sequence relies on being able to receive interrupts from
the card, in order to synchronize individual steps with the firmware.
When WED is stopped, leave interrupts running and rely on the driver turning
off unwanted ones.
WED DMA also needs to be disabled before resetting.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Refresh patches for Linux 6.1 which no longer apply cleanly after
adding patches to fix ethernet rx hang issue on MT7981/MT7986.
Fixes: ede34465de ("mediatek: fix ethernet rx hang issue on MT7981/MT7986")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-+-------------------------+-
| Model | NIC |
-+-------------------------+-
| All | MT7603 + MT7615 |
-+-------------------------+-
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Some MT7915 calibration data consists of two parts. The first part
"eeprom" size is 0xe00. The second part "precal" size is 0x19c10.
Though some devices may not have precal data, it's better to assume
that precal data exists as no users/developers confirm it. On the
other hand, some devices definitely do not contain precal data
because the EEPROM partition size is smaller than the precal NVMEM
cell size.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Innacomm W3400V6 is an xDSL B/G wireless router based on Broadcom
BCM6328 SoC.
SoC: Broadcom BCM6328
CPU: BMIPS4350 V8.0, 320 MHz, 1 core
Flash: SPI-NOR 8MB, MX25L6406E
RAM: 64 MB
Ethernet: 4x 10/100 Mbps
Switch: Integrated
Wireless: 802.11b/g, BCM4312
LEDs/Buttons: 9x / 2x
Flash instruction, web UI:
1. Set a static IP on your computer compatible with 192.168.1.1, i.e
192.168.1.100.
2. Connect the ethernet cable from your computer to the router.
3. Make sure the router is powered off.
4. Press the reset button, don't release it yet!
5. While pressing reset, power on the router.
6. Wait 10 seconds or more.
Note: The power LED is red at first then turns to solid green when
ready.
7. Release the reset button.
8. Browse to 192.168.1.1
9. Select .bin file.
10. Upgrade the image.
11. Wait for it to reboot.
Signed-off-by: Sieng-Piaw Liew <liew.s.piaw@gmail.com>
[Fix cfe nvmem-layout and pinctrl_leds indentation]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
The original configuration might be copied from bcm2710 which uses
cortex A53 rather than A72 in BCM2711, without errata might be harmful
to system stability and security.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Drop PSGMII PHY patch as it has been moved to generic in preparation for
the PHY driver to be also used for ipq807x SoC as the same PHY is also
used there.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport FIELD_PREP_CONST patch needed for at803x backport patches to
correctly compile and work.
This MACRO is needed to treat values derived from FIELD_PREP usage as
const to be used by switch case or other needed usage.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Part 1 of #13629 split.
* Sets the LAN 2 MAC address in the DTS by deriving it from LAN 1's
address. The factory OS derives this from the `eth1addr` u-boot env
variable, but the nvmem_u-boot-env driver doesn't support parsing MAC
addresses from fields other than `ethaddr`. But for all of the device
samples I've checked (~10) it derives the correct MAC.
* Updates 02_network to ensure that interfaces are assigned to roles
correctly and consistently.
Signed-off-by: Bryan Berg <bdb@north-eastham.org>
Initial backport of at803x PHY driver cleanup. This is in preparation
for split and addition of new PHY Family based on at803x needed for
ipq807x and other IPQ Series SoC.
Other affected patch are automatically refreshed with
make target/linux/refresh
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The register constants were duplicated in net/dsa/rtl83xx/debugfs.c and asm
mach-rtl838x/mach-rtl83xx.h. This commit removes this duplication.
Signed-off-by: Peter Körner <git@mazdermind.de>
According to https://svanheule.net/realtek/maple/register/led_sw_ctrl and also
drivers/net/dsa/rtl83xx/debugfs.c LED_SW_CTRL on the RTL838X should be 0xa00c
not 0x0128. Please note, that is is 0x0128 on the RTL8390/cypress SOC family.
Signed-off-by: Peter Körner <git@mazdermind.de>
the given code-format did not correctly express the condition and made the code
harder to read then necessary.
Signed-off-by: Peter Körner <git@mazdermind.de>
Fine tuning PR: openwrt/openwrt#14355 Ref: 5a82bb909b
("mediatek: GL-MT6000: Add missing LED state definitions")
As the only LED is using white in the stock firmware when the device is
running and blue for the bootloader I suggest following changes:
- Using blue for the BL and preinit+failsafe
- White for normal operation (like the original FW) and sysupgrade
With this changes it's clear by looking to the LED in which operation
mode the device is and a possible BL stuck can be seen easily.
Tested with [GL-MT6000](https://openwrt.org/toh/gl.inet/gl-mt6000).
Signed-off-by: Thomas Schröder <tschroeder_github@outlook.com>
Tested-by: Hannu Nyman <hannu.nyman@iki.fi>
Enable LED driver LP5562 on HAZE device tree and include its kernel
module package on default package for HAZE.
Signed-off-by: CheWei Chien <chewei.chien@wnc.com.tw>
Some devices (MX42CF) have a wrong MAC address configuration. The correct one is located only on the devinfo partition.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
This reduces the size of a single imagebuilder by about 40MB
In example for the target ath79 it would be the sum of generic and <target> directories, so about 16MB,
instead of the whole size of the target directory, about 53MB:
11M target/linux/generic/
3.9M target/linux/ath79/
Signed-off-by: a-gave <agave@dracaena.it>
The nvmem-cells is deprecated. Also simplify mac address settings.
Fixes: b4086f4 ("mediatek: add support for YunCore AX835")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
The mac address of the network port under the switch is
the same as the corresponding gmac by default, so there
is no need to repeat the setting. Compile test only.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
The GS110TUP v1 is a managed switch similar to the GS110TPP v1, but with
port 10 as SFP instead of RJ-45 and a total budget of 240 watts. Ports
1-4 support 60-watt 802.3bt PoE and ports 5-8 support 30-watt 802.3at.
The flash layout of the two switches are identical, and the U-Boot
configurations are the same except for having a different magic number,
so installation can be done via the same U-Boot method.
The following command will be needed to enable the port LEDs as per
https://forum.openwrt.org/t/72510/51 :
fw_setenv bootcmd "rtk network on; boota"
Additionally, port 9 (1000base-T from a separate QSGMII PHY) does not
function without this. Port 10 was not tested as no SFP module was
available.
Signed-off-by: Jacob Potter <jacob@j4cbo.com>
[rebase on merged flash layout]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.
Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Read back the reset register in order to flush the cache. This fixes
spurious reboot hangs on TP-Link TL-WDR3600 and TL-WDR4300 with Zentel
DRAM chips.
This issue was fixed in the past, but switching to the reset-driver
specific implementation removed the cache barrier which was previously
implicitly added by reading back the register in question.
Link: https://github.com/freifunk-gluon/gluon/issues/2904
Link: https://github.com/openwrt/openwrt/issues/13043
Link: https://dev.archive.openwrt.org/ticket/17839
Link: f8a7bfe1cb2c ("MIPS: ath79: fix system restart")
Signed-off-by: David Bauer <mail@david-bauer.net>
TP-Link RE365 is a wireless range extender, hardware-wise resembles
RE305 with slight changes regarding buttons and LEDs.
Specification
SoC: MediaTek MT7628AN
RAM: 64 MiB DDR2
Flash: 8 MiB SPI NOR
WiFi: 2.4 GHz 2T2R integrated
5 GHz 2T2R MediaTek MT7612EN conncted to PCIe lanes
Ethernet: 1x 10/100 Mbps integrated
LEDs: 6x GPIO controlled
Buttons: 4x GPIO controlled
UART: row of 4 holes marked on PCB as J1, starting count from white
triangle
1. VCC (3.3V), 2. GND, 3. RX, 4. TX
baud: 57600, parity: none, flow control: none
Installation
1. Open web management interface.
2. Go to Settings > System Tools > Firmware upgrade.
3. Select "Browse" and select the OpenWrt image with factory.bin suffix.
4. After selecting "Upgrade" firmware writing process will start.
5. Wait till device reboots, power LED should stay solid when it's fully
booted, then it's ready for configuration through LAN port.
Additional information
With how device manufacturer patrtitioned the flash memory, it's possible
that with default packages set, initial factory.bin image won't be
created. In such case, try to reduce packages amount or use older release
for initial conversion to OpenWrt. Later You can use sysupgrade.bin
image with full set of packages because OpenWrt uses unpartitioned flash
memory space unused by vendor firmware.
Reverting to vendor firmware involves converting firmware using
tplink-safeloader with -z option (can be found in ImageBuilder or SDK)
and forcibly applying converted firmware as sysupgrade.
Known issues
WARNING: after removing casing of the device one is exposed to high
voltage and is in a risk of being electrocuted.
Caution when interfacing whith bootloader, saving its environment either
by issuing "saveenv" or selecting option "1: Load system code to SDRAM
via TFTP." in boot menu, any of those will lead to overwriting part of
kernel. This will lead to need of firmware recovery. The cause of this
issue is bootloader having environment offset on flash at 0x40000,
while kernel starts from 0x20000.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
[Wrap long line in DTS]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before, PVID is reset for all ports and goes out of bounds. Also, PVID
is later changed by dsa configuration by `ip link` and `bridge vlan`
commands, this does not change the CPU port PVID and CPU PVID stays 0.
It does not allow sending packets from OpenWrt to any connected devices
unless default configuration is changed
This change iterates up to and including cpu_port and sets default PVID
to 1. For lan* ports PVID can be configured with `ip link` and `bridge
vlan` commands
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Fix incorrect register value being set for VLAN_PORT_FWD
Before, the 0b1111 would be set for the register which means outgoing
packets would receive an extra tag, corresponding to the PVID of the
port.
On untagged ports, this meant outgoing packets with a single tag.
On tagged ports, this meant outgoing QinQ packets, where the inner tag
was either the PVID of the untagged ingress port, or the already
assigned original (single) tag.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Without this, luci shows 10M full duplex when there is no link. So
explicitly set half duplex and unknown speed.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Use led_setX to determine number of LEDs per port. Introduce macros to
calculate register value and shift for particular LED in a particular
set.
Problem with previous implementation is that it uses is10G status to
determine leds per port. However with usxgmii, driver sets 10g, 5g and
2.5g so even though there are only 2 leds per port it selects 4 leds per
port
This implementation relies on configured led_set node.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
