diff --git a/target/linux/airoha/an7581/config-6.6 b/target/linux/airoha/an7581/config-6.6 index f80bf49f8c1..d86aa8bbbbb 100644 --- a/target/linux/airoha/an7581/config-6.6 +++ b/target/linux/airoha/an7581/config-6.6 @@ -1,4 +1,5 @@ CONFIG_64BIT=y +CONFIG_AIROHA_CPU_PM_DOMAIN=y CONFIG_AIROHA_THERMAL=y CONFIG_AIROHA_WATCHDOG=y CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y diff --git a/target/linux/airoha/dts/an7581.dtsi b/target/linux/airoha/dts/an7581.dtsi index 820ab0bfa8f..2b4c1b716be 100644 --- a/target/linux/airoha/dts/an7581.dtsi +++ b/target/linux/airoha/dts/an7581.dtsi @@ -81,7 +81,7 @@ clocks = <&cpufreq>; clock-names = "cpu"; power-domains = <&cpufreq>; - power-domain-names = "cpu_pd"; + power-domain-names = "perf"; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -95,7 +95,7 @@ clocks = <&cpufreq>; clock-names = "cpu"; power-domains = <&cpufreq>; - power-domain-names = "cpu_pd"; + power-domain-names = "perf"; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -109,7 +109,7 @@ clocks = <&cpufreq>; clock-names = "cpu"; power-domains = <&cpufreq>; - power-domain-names = "cpu_pd"; + power-domain-names = "perf"; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -123,7 +123,7 @@ clocks = <&cpufreq>; clock-names = "cpu"; power-domains = <&cpufreq>; - power-domain-names = "cpu_pd"; + power-domain-names = "perf"; next-level-cache = <&l2>; #cooling-cells = <2>; }; diff --git a/target/linux/airoha/patches-6.6/100-02-cpufreq-airoha-Add-EN7581-CPUFreq-SMCCC-driver.patch b/target/linux/airoha/patches-6.6/039-v6.14-cpufreq-airoha-Add-EN7581-CPUFreq-SMCCC-driver.patch similarity index 83% rename from target/linux/airoha/patches-6.6/100-02-cpufreq-airoha-Add-EN7581-CPUFreq-SMCCC-driver.patch rename to target/linux/airoha/patches-6.6/039-v6.14-cpufreq-airoha-Add-EN7581-CPUFreq-SMCCC-driver.patch index 6a2e54f4d1a..0db82d55e14 100644 --- a/target/linux/airoha/patches-6.6/100-02-cpufreq-airoha-Add-EN7581-CPUFreq-SMCCC-driver.patch +++ b/target/linux/airoha/patches-6.6/039-v6.14-cpufreq-airoha-Add-EN7581-CPUFreq-SMCCC-driver.patch @@ -1,7 +1,7 @@ -From fa27cb99b297a1a9c0a5824afe5a670e424fff61 Mon Sep 17 00:00:00 2001 +From 84cf9e541cccb8cb698518a9897942e8c78f1d83 Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Wed, 16 Oct 2024 18:00:57 +0200 -Subject: [PATCH v9 2/2] cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver +Date: Thu, 9 Jan 2025 14:12:58 +0100 +Subject: [PATCH] cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver Add simple CPU Freq driver for Airoha EN7581 SoC that control CPU frequency scaling with SMC APIs and register a generic "cpufreq-dt" @@ -14,29 +14,8 @@ Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq driver is needed with OPP v2 nodes declared in DTS. Signed-off-by: Christian Marangi +Signed-off-by: Viresh Kumar --- -Changes v9: -- Fix compile error targetting wrong branch (remove_new change and new PM OPs) -Changes v8: -- Split in dedicated PM domain driver -Changes v7: -- No changes -Changes v6: -- Improve Kconfig depends logic -- Select PM (PM_GENERIC_DOMAINS depends on it) -- Drop (int) cast for -Changes v5: -- Rename cpu_pd to perf for power domain name -- Use remove instead of remove_new -Changes v4: -- Rework to clk-only + PM set_performance_state implementation -Changes v3: -- Adapt to new cpufreq-dt APIs -- Register cpufreq-dt instead of custom freq driver -Changes v2: -- Fix kernel bot error with missing slab.h and bitfield.h header -- Limit COMPILE_TEST to ARM64 due to smcc 1.2 - drivers/cpufreq/Kconfig.arm | 8 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/airoha-cpufreq.c | 152 +++++++++++++++++++++++++++ @@ -104,11 +83,15 @@ Changes v2: +} + +static const char * const airoha_cpufreq_clk_names[] = { "cpu", NULL }; -+static const char * const airoha_cpufreq_genpd_names[] = { "cpu_pd", NULL }; ++static const char * const airoha_cpufreq_pd_names[] = { "perf", NULL }; + +static int airoha_cpufreq_probe(struct platform_device *pdev) +{ -+ struct dev_pm_opp_config config = { }; ++ struct dev_pm_opp_config config = { ++ .clk_names = airoha_cpufreq_clk_names, ++ .config_clks = airoha_cpufreq_config_clks_nop, ++ .genpd_names = airoha_cpufreq_pd_names, ++ }; + struct platform_device *cpufreq_dt; + struct airoha_cpufreq_priv *priv; + struct device *dev = &pdev->dev; @@ -125,18 +108,14 @@ Changes v2: + if (!priv) + return -ENOMEM; + -+ config.clk_names = airoha_cpufreq_clk_names; -+ config.config_clks = airoha_cpufreq_config_clks_nop; -+ config.genpd_names = airoha_cpufreq_genpd_names; -+ config.virt_devs = &virt_devs; -+ ++ /* Set OPP table conf with NOP config_clks */ + priv->opp_token = dev_pm_opp_set_config(cpu_dev, &config); + if (priv->opp_token < 0) + return dev_err_probe(dev, priv->opp_token, "Failed to set OPP config\n"); + + /* Set Attached PM for OPP ACTIVE */ + if (virt_devs) { -+ const char * const *name = airoha_cpufreq_genpd_names; ++ const char * const *name = airoha_cpufreq_pd_names; + int i, j; + + for (i = 0; *name; i++, name++) { @@ -177,7 +156,7 @@ Changes v2: +static void airoha_cpufreq_remove(struct platform_device *pdev) +{ + struct airoha_cpufreq_priv *priv = platform_get_drvdata(pdev); -+ const char * const *name = airoha_cpufreq_genpd_names; ++ const char * const *name = airoha_cpufreq_pd_names; + int i; + + platform_device_unregister(priv->cpufreq_dt); diff --git a/target/linux/airoha/patches-6.6/100-01-pmdomain-airoha-Add-Airoha-CPU-PM-Domain-support.patch b/target/linux/airoha/patches-6.6/040-v6.14-pmdomain-airoha-Add-Airoha-CPU-PM-Domain-support.patch similarity index 83% rename from target/linux/airoha/patches-6.6/100-01-pmdomain-airoha-Add-Airoha-CPU-PM-Domain-support.patch rename to target/linux/airoha/patches-6.6/040-v6.14-pmdomain-airoha-Add-Airoha-CPU-PM-Domain-support.patch index 52d3f40b369..8dc8a3d304a 100644 --- a/target/linux/airoha/patches-6.6/100-01-pmdomain-airoha-Add-Airoha-CPU-PM-Domain-support.patch +++ b/target/linux/airoha/patches-6.6/040-v6.14-pmdomain-airoha-Add-Airoha-CPU-PM-Domain-support.patch @@ -1,7 +1,7 @@ -From 76e4e6ce9aaae897f80e375345bf0095e1b09ff2 Mon Sep 17 00:00:00 2001 +From 82e703dd438b71432cc0ccbb90925d1e32dd014a Mon Sep 17 00:00:00 2001 From: Christian Marangi -Date: Sat, 4 Jan 2025 19:03:09 +0100 -Subject: [PATCH v9 1/2] pmdomain: airoha: Add Airoha CPU PM Domain support +Date: Thu, 9 Jan 2025 14:12:57 +0100 +Subject: [PATCH] pmdomain: airoha: Add Airoha CPU PM Domain support Add Airoha CPU PM Domain support to control frequency and power of CPU present on Airoha EN7581 SoC. @@ -11,25 +11,21 @@ passing the performance state. The driver also expose a read-only clock that expose the current CPU frequency with SMC command. Signed-off-by: Christian Marangi +Link: https://lore.kernel.org/r/20250109131313.32317-1-ansuelsmth@gmail.com +Signed-off-by: Ulf Hansson --- -Changes v9: -- Fix compile error targetting wrong branch (remove_new change) -Changes v8: -- Add this patch -- Use SMC invoke instead of 1.2 - - drivers/pmdomain/mediatek/Kconfig | 11 ++ + drivers/pmdomain/mediatek/Kconfig | 12 ++ drivers/pmdomain/mediatek/Makefile | 1 + .../pmdomain/mediatek/airoha-cpu-pmdomain.c | 144 ++++++++++++++++++ - 3 files changed, 156 insertions(+) + 3 files changed, 157 insertions(+) create mode 100644 drivers/pmdomain/mediatek/airoha-cpu-pmdomain.c --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig -@@ -72,6 +72,17 @@ config MTK_SCPSYS_PM_DOMAINS - Control Processor System (SCPSYS) has several power management related - tasks in the system. - +@@ -2,6 +2,17 @@ + # + # MediaTek SoC drivers + # +config AIROHA_CPU_PM_DOMAIN + tristate "Airoha CPU power domain" + default ARCH_AIROHA @@ -41,9 +37,9 @@ Changes v8: + CPU frequency and power is controlled by ATF with SMC command to + set performance states. + - config MTK_MMSYS - tristate "MediaTek MMSYS Support" - default ARCH_MEDIATEK + menu "MediaTek SoC drivers" + depends on ARCH_MEDIATEK || COMPILE_TEST + --- a/drivers/pmdomain/mediatek/Makefile +++ b/drivers/pmdomain/mediatek/Makefile @@ -1,3 +1,4 @@ @@ -53,7 +49,7 @@ Changes v8: +obj-$(CONFIG_AIROHA_CPU_PM_DOMAIN) += airoha-cpu-pmdomain.o --- /dev/null +++ b/drivers/pmdomain/mediatek/airoha-cpu-pmdomain.c -@@ -0,0 +1,145 @@ +@@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include @@ -123,9 +119,13 @@ Changes v8: +{ + struct airoha_cpu_pmdomain_priv *priv; + struct device *dev = &pdev->dev; -+ struct clk_init_data init = { }; ++ const struct clk_init_data init = { ++ .name = "cpu", ++ .ops = &airoha_cpu_pmdomain_clk_ops, ++ /* Clock with no set_rate, can't cache */ ++ .flags = CLK_GET_RATE_NOCACHE, ++ }; + struct generic_pm_domain *pd; -+ struct clk_hw *hw; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -133,18 +133,13 @@ Changes v8: + return -ENOMEM; + + /* Init and register a get-only clk for Cpufreq */ -+ init.name = "cpu"; -+ init.ops = &airoha_cpu_pmdomain_clk_ops; -+ /* Clock with no set_rate, can't cache */ -+ init.flags = CLK_GET_RATE_NOCACHE; -+ -+ hw = &priv->hw; -+ hw->init = &init; -+ ret = devm_clk_hw_register(dev, hw); ++ priv->hw.init = &init; ++ ret = devm_clk_hw_register(dev, &priv->hw); + if (ret) + return ret; + -+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, ++ &priv->hw); + if (ret) + return ret; +