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ramips: replace mt7621s hack with upstream patch
Refresh patches. Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core MT7621 device (Netgear R6220). This change will make future kernel upgrades easier (avoids conflicts with upstream). Link: https://lore.kernel.org/lkml/20210407200738.149207-1-ilya.lipnitskiy@gmail.com/ Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Cc: Chuanhong Guo <gch981213@gmail.com>
This commit is contained in:
Ilya Lipnitskiy
Hauke Mehrtens
parent
17e690017d
commit
fa6f57f66c
@ -0,0 +1,74 @@
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From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
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From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
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Date: Wed, 7 Apr 2021 13:07:38 -0700
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Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
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Most MT7621 SoCs have 2 cores, which is detected and supported properly
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by CPS.
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Unfortunately, MT7621 SoC has a less common S variant with only one core.
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On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
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starting SMP. CPULAUNCH registers can be used in that case to detect the
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absence of the second core and override the GCR_CONFIG PCORES field.
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Rework a long-standing OpenWrt patch to override the value of
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mips_cps_numcores on single-core MT7621 systems.
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Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
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MT7621 device (Netgear R6220).
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Original 4.14 OpenWrt patch:
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Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
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Current 5.10 OpenWrt patch:
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Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
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Suggested-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
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1 file changed, 22 insertions(+), 1 deletion(-)
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--- a/arch/mips/include/asm/mips-cps.h
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+++ b/arch/mips/include/asm/mips-cps.h
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@@ -10,6 +10,8 @@
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#include <linux/io.h>
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#include <linux/types.h>
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+#include <asm/mips-boards/launch.h>
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+
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extern unsigned long __cps_access_bad_size(void)
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__compiletime_error("Bad size for CPS accessor");
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@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_
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*/
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static inline unsigned int mips_cps_numcores(unsigned int cluster)
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{
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+ unsigned int ncores;
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+
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if (!mips_cm_present())
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return 0;
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/* Add one before masking to handle 0xff indicating no cores */
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- return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
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+ ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
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+
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+ if (IS_ENABLED(CONFIG_SOC_MT7621)) {
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+ struct cpulaunch *launch;
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+
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+ /*
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+ * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
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+ * always reports 2 cores. Check the second core's LAUNCH_FREADY
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+ * flag to detect if the second core is missing. This method
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+ * only works before the core has been started.
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+ */
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+ launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
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+ launch += 2; /* MT7621 has 2 VPEs per core */
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+ if (!(launch->flags & LAUNCH_FREADY))
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+ ncores = 1;
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+ }
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+
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+ return ncores;
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}
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/**
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@ -1,61 +0,0 @@
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There is a variant of MT7621 which contains only one CPU core instead of 2.
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This is not reflected in the config register, so the kernel detects more
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physical cores, which leads to a hang on SMP bringup.
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Add a hack to detect missing cores.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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--- a/arch/mips/kernel/smp-cps.c
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+++ b/arch/mips/kernel/smp-cps.c
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@@ -43,6 +43,11 @@ static unsigned core_vpe_count(unsigned
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return mips_cps_numvps(cluster, core);
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}
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+bool __weak plat_cpu_core_present(int core)
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+{
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+ return true;
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+}
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+
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static void __init cps_smp_setup(void)
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{
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unsigned int nclusters, ncores, nvpes, core_vpes;
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@@ -60,6 +65,8 @@ static void __init cps_smp_setup(void)
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ncores = mips_cps_numcores(cl);
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for (c = 0; c < ncores; c++) {
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+ if (!plat_cpu_core_present(c))
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+ continue;
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core_vpes = core_vpe_count(cl, c);
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if (c > 0)
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -15,6 +15,7 @@
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#include <asm/mips-cps.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7621.h>
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+#include <asm/mips-boards/launch.h>
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#include <pinmux.h>
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@@ -146,6 +147,20 @@ static void soc_dev_init(struct ralink_s
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}
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}
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+bool plat_cpu_core_present(int core)
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+{
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+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
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+
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+ if (!core)
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+ return true;
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+ launch += core * 2; /* 2 VPEs per core */
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+ if (!(launch->flags & LAUNCH_FREADY))
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+ return false;
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+ if (launch->flags & (LAUNCH_FGO | LAUNCH_FGONE))
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+ return false;
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+ return true;
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+}
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+
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
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@ -36,7 +36,7 @@
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#define MT7621_DDR2_SIZE_MAX 256
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -9,6 +9,10 @@
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@@ -9,12 +9,17 @@
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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@ -47,15 +47,14 @@
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#include <asm/mipsregs.h>
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#include <asm/smp-ops.h>
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@@ -16,6 +20,7 @@
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#include <asm/mips-cps.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7621.h>
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#include <asm/mips-boards/launch.h>
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+#include <asm/time.h>
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#include <pinmux.h>
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@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
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@@ -105,11 +110,89 @@ static struct rt2880_pmx_group mt7621_pi
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{ 0 }
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};
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@ -58,7 +58,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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#include <asm/mipsregs.h>
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#include <asm/smp-ops.h>
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#include <asm/mips-cps.h>
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@@ -55,6 +57,8 @@
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@@ -54,6 +56,8 @@
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#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
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#define MT7621_GPIO_MODE_SDHCI_GPIO 1
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@ -67,7 +67,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
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static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
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static struct rt2880_pmx_func uart3_grp[] = {
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@@ -139,6 +143,26 @@ static struct clk *__init mt7621_add_sys
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@@ -138,6 +142,26 @@ static struct clk *__init mt7621_add_sys
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return clk;
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}
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@ -94,7 +94,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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void __init ralink_clk_init(void)
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{
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u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
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@@ -292,10 +316,7 @@ void prom_soc_init(struct ralink_soc_inf
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@@ -277,10 +301,7 @@ void prom_soc_init(struct ralink_soc_inf
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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