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layerscape: enable spi-uart in LS1012A-FRDM

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This patch add missing support of SC16IS740 serial controller, installed
on LS1012A-FRDM board.

It was required to change RCW bits, because SPI was disabled by default.

Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: maurerr <mariusd84@gmail.com>
This commit is contained in:
Pawel Dembicki 2020-11-04 10:16:31 +01:00 committed by maurerr
parent d75b75ab5a
commit fa2bb97c20
4 changed files with 76 additions and 1 deletions
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2
package/firmware/layerscape/ls-rcw/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=ls-rcw PKG_NAME:=ls-rcw
PKG_VERSION:=LSDK-20.04-update-290520 PKG_VERSION:=LSDK-20.04-update-290520
PKG_RELEASE:=1 PKG_RELEASE:=2
PKG_SOURCE_PROTO:=git PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/rcw PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/rcw

13
package/firmware/layerscape/ls-rcw/patches/0002-fix_rcw_for_ls1012a-frdm.patch Normal file
View File

@ -0,0 +1,13 @@
--- a/ls1012afrdm/N_SSNP_3305/rcw_800.rcw
+++ b/ls1012afrdm/N_SSNP_3305/rcw_800.rcw
@@ -41,8 +41,8 @@ EC1_EXT_SAI2_RX=1
EC1_BASE=0
UART1_BASE=1
SDHC1_BASE=1
-SDHC2_BASE_DAT321=1
-SDHC2_BASE_BASE=1
+SDHC2_BASE_DAT321=3
+SDHC2_BASE_BASE=3
UART2_BASE_DATA=1
EMI1_BASE=1
CLK_OUT_BASE=1

4
target/linux/layerscape/armv8_64b/config-5.4
View File

@ -842,6 +842,10 @@ CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_SC16IS7XX=y
CONFIG_SERIAL_SC16IS7XX_CORE=y
# CONFIG_SERIAL_SC16IS7XX_I2C is not set
CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
CONFIG_SERIO=y CONFIG_SERIO=y

58
target/linux/layerscape/patches-5.4/902-layerscape_improve_support_of_LS1012A-FRDM.patch Normal file
View File

@ -0,0 +1,58 @@
From 12de4b5e7cbcd193d5abb753ca511fe8f2236846 Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Fri, 13 Nov 2020 07:30:03 +0100
Subject: [PATCH 2/2] arm64: dts: fsl-ls1012a-frdm: add spi-uart device
This patch adds spi-uart controller to LS1012A-FRDM board dts.
Device is equipped in SC16IS740 from NXP.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
.../boot/dts/freescale/fsl-ls1012a-frdm.dts | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -7,6 +7,7 @@
*/
/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
#include "fsl-ls1012a.dtsi"
/ {
@@ -16,6 +17,7 @@
aliases {
ethernet0 = &pfe_mac0;
ethernet1 = &pfe_mac1;
+ serial0 = &duart0;
};
sys_mclk: clock-mclk {
@@ -61,6 +63,26 @@
};
};
};
+
+&dspi {
+ status = "okay";
+ bus-num = <0>;
+
+ serial@0 {
+ reg = <0>;
+ compatible = "nxp,sc16is740";
+ spi-max-frequency = <4000000>;
+ clocks = <&sc16is7xx_clk>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+ sc16is7xx_clk: sc16is7xx_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+};
&duart0 {
status = "okay";