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generic: 5.15: backport qca8k fixup for mgmt and mdio read/write
Backport qca8k fixup for mgmt and mdio read/write for kernel 5.15 fixup port dropping and configuration issue. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Christian Marangi
parent
68f983ba41
commit
f4d949b404
@ -0,0 +1,102 @@
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From 9807ae69746196ee4bbffe7d22d22ab2b61c6ed0 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 29 Dec 2022 17:33:32 +0100
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Subject: [PATCH 1/5] net: dsa: qca8k: fix wrong length value for mgmt eth
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packet
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The assumption that Documentation was right about how this value work was
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wrong. It was discovered that the length value of the mgmt header is in
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step of word size.
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As an example to process 4 byte of data the correct length to set is 2.
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To process 8 byte 4, 12 byte 6, 16 byte 8...
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Odd values will always return the next size on the ack packet.
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(length of 3 (6 byte) will always return 8 bytes of data)
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This means that a value of 15 (0xf) actually means reading/writing 32 bytes
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of data instead of 16 bytes. This behaviour is totally absent and not
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documented in the switch Documentation.
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In fact from Documentation the max value that mgmt eth can process is
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16 byte of data while in reality it can process 32 bytes at once.
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To handle this we always round up the length after deviding it for word
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size. We check if the result is odd and we round another time to align
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to what the switch will provide in the ack packet.
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The workaround for the length limit of 15 is still needed as the length
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reg max value is 0xf(15)
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Reported-by: Ronald Wahl <ronald.wahl@raritan.com>
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Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
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Fixes: 90386223f44e ("net: dsa: qca8k: add support for larger read/write size with mgmt Ethernet")
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Cc: stable@vger.kernel.org # v5.18+
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 45 +++++++++++++++++++++++++-------
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1 file changed, 35 insertions(+), 10 deletions(-)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -146,7 +146,16 @@ static void qca8k_rw_reg_ack_handler(str
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command = get_unaligned_le32(&mgmt_ethhdr->command);
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cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command);
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+
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len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command);
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+ /* Special case for len of 15 as this is the max value for len and needs to
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+ * be increased before converting it from word to dword.
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+ */
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+ if (len == 15)
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+ len++;
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+
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+ /* We can ignore odd value, we always round up them in the alloc function. */
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+ len *= sizeof(u16);
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/* Make sure the seq match the requested packet */
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if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq)
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@@ -193,17 +202,33 @@ static struct sk_buff *qca8k_alloc_mdio_
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if (!skb)
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return NULL;
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- /* Max value for len reg is 15 (0xf) but the switch actually return 16 byte
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- * Actually for some reason the steps are:
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- * 0: nothing
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- * 1-4: first 4 byte
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- * 5-6: first 12 byte
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- * 7-15: all 16 byte
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+ /* Hdr mgmt length value is in step of word size.
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+ * As an example to process 4 byte of data the correct length to set is 2.
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+ * To process 8 byte 4, 12 byte 6, 16 byte 8...
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+ *
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+ * Odd values will always return the next size on the ack packet.
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+ * (length of 3 (6 byte) will always return 8 bytes of data)
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+ *
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+ * This means that a value of 15 (0xf) actually means reading/writing 32 bytes
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+ * of data.
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+ *
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+ * To correctly calculate the length we devide the requested len by word and
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+ * round up.
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+ * On the ack function we can skip the odd check as we already handle the
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+ * case here.
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*/
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- if (len == 16)
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- real_len = 15;
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- else
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- real_len = len;
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+ real_len = DIV_ROUND_UP(len, sizeof(u16));
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+
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+ /* We check if the result len is odd and we round up another time to
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+ * the next size. (length of 3 will be increased to 4 as switch will always
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+ * return 8 bytes)
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+ */
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+ if (real_len % sizeof(u16) != 0)
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+ real_len++;
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+
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+ /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */
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+ if (real_len == 16)
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+ real_len--;
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skb_reset_mac_header(skb);
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skb_set_network_header(skb, skb->len);
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@ -0,0 +1,34 @@
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From d9dba91be71f03cc75bcf39fc0d5d99ff33f1ae0 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 29 Dec 2022 17:33:33 +0100
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Subject: [PATCH 2/5] net: dsa: tag_qca: fix wrong MGMT_DATA2 size
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It was discovered that MGMT_DATA2 can contain up to 28 bytes of data
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instead of the 12 bytes written in the Documentation by accounting the
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limit of 16 bytes declared in Documentation subtracting the first 4 byte
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in the packet header.
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Update the define with the real world value.
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Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
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Fixes: c2ee8181fddb ("net: dsa: tag_qca: add define for handling mgmt Ethernet packet")
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Cc: stable@vger.kernel.org # v5.18+
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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include/linux/dsa/tag_qca.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/include/linux/dsa/tag_qca.h
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+++ b/include/linux/dsa/tag_qca.h
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@@ -40,8 +40,8 @@
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QCA_HDR_MGMT_COMMAND_LEN + \
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QCA_HDR_MGMT_DATA1_LEN)
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-#define QCA_HDR_MGMT_DATA2_LEN 12 /* Other 12 byte for the mdio data */
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-#define QCA_HDR_MGMT_PADDING_LEN 34 /* Padding to reach the min Ethernet packet */
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+#define QCA_HDR_MGMT_DATA2_LEN 28 /* Other 28 byte for the mdio data */
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+#define QCA_HDR_MGMT_PADDING_LEN 18 /* Padding to reach the min Ethernet packet */
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#define QCA_HDR_MGMT_PKT_LEN (QCA_HDR_MGMT_HEADER_LEN + \
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QCA_HDR_LEN + \
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@ -0,0 +1,172 @@
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From 03cb9e6d0b32b768e3d9d473c5c4ca1100877664 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 29 Dec 2022 17:33:34 +0100
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Subject: [PATCH 3/5] Revert "net: dsa: qca8k: cache lo and hi for mdio write"
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This reverts commit 2481d206fae7884cd07014fd1318e63af35e99eb.
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The Documentation is very confusing about the topic.
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The cache logic for hi and lo is wrong and actually miss some regs to be
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actually written.
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What the Documentation actually intended was that it's possible to skip
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writing hi OR lo if half of the reg is not needed to be written or read.
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Revert the change in favor of a better and correct implementation.
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Reported-by: Ronald Wahl <ronald.wahl@raritan.com>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Cc: stable@vger.kernel.org # v5.18+
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 61 +++++++-------------------------
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drivers/net/dsa/qca/qca8k.h | 5 ---
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2 files changed, 12 insertions(+), 54 deletions(-)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -37,44 +37,6 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
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}
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static int
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-qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
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-{
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- u16 *cached_lo = &priv->mdio_cache.lo;
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- struct mii_bus *bus = priv->bus;
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- int ret;
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-
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- if (lo == *cached_lo)
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- return 0;
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-
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- ret = bus->write(bus, phy_id, regnum, lo);
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- if (ret < 0)
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- dev_err_ratelimited(&bus->dev,
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- "failed to write qca8k 32bit lo register\n");
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-
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- *cached_lo = lo;
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- return 0;
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-}
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-
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-static int
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-qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
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-{
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- u16 *cached_hi = &priv->mdio_cache.hi;
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- struct mii_bus *bus = priv->bus;
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- int ret;
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-
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- if (hi == *cached_hi)
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- return 0;
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-
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- ret = bus->write(bus, phy_id, regnum, hi);
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- if (ret < 0)
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- dev_err_ratelimited(&bus->dev,
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- "failed to write qca8k 32bit hi register\n");
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-
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- *cached_hi = hi;
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- return 0;
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-}
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-
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-static int
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qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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{
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int ret;
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@@ -97,7 +59,7 @@ qca8k_mii_read32(struct mii_bus *bus, in
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}
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static void
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-qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
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+qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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{
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u16 lo, hi;
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int ret;
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@@ -105,9 +67,12 @@ qca8k_mii_write32(struct qca8k_priv *pri
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lo = val & 0xffff;
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hi = (u16)(val >> 16);
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- ret = qca8k_set_lo(priv, phy_id, regnum, lo);
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+ ret = bus->write(bus, phy_id, regnum, lo);
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if (ret >= 0)
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- ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
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+ ret = bus->write(bus, phy_id, regnum + 1, hi);
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+ if (ret < 0)
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to write qca8k 32bit register\n");
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}
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static int
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@@ -442,7 +407,7 @@ qca8k_regmap_write(void *ctx, uint32_t r
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if (ret < 0)
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goto exit;
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- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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exit:
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mutex_unlock(&bus->mdio_lock);
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@@ -475,7 +440,7 @@ qca8k_regmap_update_bits(void *ctx, uint
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val &= ~mask;
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val |= write_val;
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- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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exit:
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mutex_unlock(&bus->mdio_lock);
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@@ -750,14 +715,14 @@ qca8k_mdio_write(struct qca8k_priv *priv
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if (ret)
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goto exit;
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- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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exit:
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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- qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
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+ qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
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mutex_unlock(&bus->mdio_lock);
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@@ -787,7 +752,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
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if (ret)
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goto exit;
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- qca8k_mii_write32(priv, 0x10 | r2, r1, val);
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+ qca8k_mii_write32(bus, 0x10 | r2, r1, val);
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ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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@@ -798,7 +763,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,
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exit:
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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- qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
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+ qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
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mutex_unlock(&bus->mdio_lock);
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@@ -1914,8 +1879,6 @@ qca8k_sw_probe(struct mdio_device *mdiod
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}
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priv->mdio_cache.page = 0xffff;
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- priv->mdio_cache.lo = 0xffff;
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- priv->mdio_cache.hi = 0xffff;
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/* Check the detected switch id */
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ret = qca8k_read_switch_id(priv);
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--- a/drivers/net/dsa/qca/qca8k.h
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+++ b/drivers/net/dsa/qca/qca8k.h
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@@ -375,11 +375,6 @@ struct qca8k_mdio_cache {
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* mdio writes
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*/
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u16 page;
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-/* lo and hi can also be cached and from Documentation we can skip one
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- * extra mdio write if lo or hi is didn't change.
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- */
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- u16 lo;
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- u16 hi;
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};
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struct qca8k_priv {
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@ -0,0 +1,150 @@
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From cfbd6de588ef659c198083205dc954a6d3ed2aec Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 29 Dec 2022 17:33:35 +0100
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Subject: [PATCH 4/5] net: dsa: qca8k: introduce single mii read/write lo/hi
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It may be useful to read/write just the lo or hi half of a reg.
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This is especially useful for phy poll with the use of mdio master.
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The mdio master reg is composed by the first 16 bit related to setup and
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the other half with the returned data or data to write.
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Refactor the mii function to permit single mii read/write of lo or hi
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half of the reg.
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Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 106 ++++++++++++++++++++++++-------
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1 file changed, 84 insertions(+), 22 deletions(-)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -37,42 +37,104 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u
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}
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static int
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-qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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+qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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{
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int ret;
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+ u16 lo;
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- ret = bus->read(bus, phy_id, regnum);
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- if (ret >= 0) {
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- *val = ret;
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- ret = bus->read(bus, phy_id, regnum + 1);
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- *val |= ret << 16;
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- }
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+ lo = val & 0xffff;
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+ ret = bus->write(bus, phy_id, regnum, lo);
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+ if (ret < 0)
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to write qca8k 32bit lo register\n");
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+
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+ return ret;
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+}
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- if (ret < 0) {
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+static int
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+qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
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+{
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+ int ret;
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+ u16 hi;
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+
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+ hi = (u16)(val >> 16);
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+ ret = bus->write(bus, phy_id, regnum, hi);
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+ if (ret < 0)
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dev_err_ratelimited(&bus->dev,
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- "failed to read qca8k 32bit register\n");
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- *val = 0;
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- return ret;
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- }
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+ "failed to write qca8k 32bit hi register\n");
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+ return ret;
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+}
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+
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+static int
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+qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
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+{
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+ int ret;
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+
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+ ret = bus->read(bus, phy_id, regnum);
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+ if (ret < 0)
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+ goto err;
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+
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+ *val = ret & 0xffff;
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return 0;
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+
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+err:
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+ dev_err_ratelimited(&bus->dev,
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+ "failed to read qca8k 32bit lo register\n");
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+ *val = 0;
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+
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+ return ret;
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}
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|
||||
-static void
|
||||
-qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
|
||||
+static int
|
||||
+qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
|
||||
{
|
||||
- u16 lo, hi;
|
||||
int ret;
|
||||
|
||||
- lo = val & 0xffff;
|
||||
- hi = (u16)(val >> 16);
|
||||
+ ret = bus->read(bus, phy_id, regnum);
|
||||
+ if (ret < 0)
|
||||
+ goto err;
|
||||
|
||||
- ret = bus->write(bus, phy_id, regnum, lo);
|
||||
- if (ret >= 0)
|
||||
- ret = bus->write(bus, phy_id, regnum + 1, hi);
|
||||
+ *val = ret << 16;
|
||||
+ return 0;
|
||||
+
|
||||
+err:
|
||||
+ dev_err_ratelimited(&bus->dev,
|
||||
+ "failed to read qca8k 32bit hi register\n");
|
||||
+ *val = 0;
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
|
||||
+{
|
||||
+ u32 hi, lo;
|
||||
+ int ret;
|
||||
+
|
||||
+ *val = 0;
|
||||
+
|
||||
+ ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo);
|
||||
if (ret < 0)
|
||||
- dev_err_ratelimited(&bus->dev,
|
||||
- "failed to write qca8k 32bit register\n");
|
||||
+ goto err;
|
||||
+
|
||||
+ ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi);
|
||||
+ if (ret < 0)
|
||||
+ goto err;
|
||||
+
|
||||
+ *val = lo | hi;
|
||||
+
|
||||
+err:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
|
||||
+{
|
||||
+ if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0)
|
||||
+ return;
|
||||
+
|
||||
+ qca8k_mii_write_hi(bus, phy_id, regnum + 1, val);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -0,0 +1,73 @@
|
||||
From a4165830ca237f2b3318faf62562bce8ce12a389 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Date: Thu, 29 Dec 2022 17:33:36 +0100
|
||||
Subject: [PATCH 5/5] net: dsa: qca8k: improve mdio master read/write by using
|
||||
single lo/hi
|
||||
|
||||
Improve mdio master read/write by using singe mii read/write lo/hi.
|
||||
|
||||
In a read and write we need to poll the mdio master regs in a busy loop
|
||||
to check for a specific bit present in the upper half of the reg. We can
|
||||
ignore the other half since it won't contain useful data. This will save
|
||||
an additional useless read for each read and write operation.
|
||||
|
||||
In a read operation the returned data is present in the mdio master reg
|
||||
lower half. We can ignore the other half since it won't contain useful
|
||||
data. This will save an additional useless read for each read operation.
|
||||
|
||||
In a read operation it's needed to just set the hi half of the mdio
|
||||
master reg as the lo half will be replaced by the result. This will save
|
||||
an additional useless write for each read operation.
|
||||
|
||||
Tested-by: Ronald Wahl <ronald.wahl@raritan.com>
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/dsa/qca/qca8k-8xxx.c | 12 ++++++------
|
||||
1 file changed, 6 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
|
||||
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
|
||||
@@ -740,9 +740,9 @@ qca8k_mdio_busy_wait(struct mii_bus *bus
|
||||
|
||||
qca8k_split_addr(reg, &r1, &r2, &page);
|
||||
|
||||
- ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
|
||||
+ ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0,
|
||||
QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
|
||||
- bus, 0x10 | r2, r1, &val);
|
||||
+ bus, 0x10 | r2, r1 + 1, &val);
|
||||
|
||||
/* Check if qca8k_read has failed for a different reason
|
||||
* before returnting -ETIMEDOUT
|
||||
@@ -784,7 +784,7 @@ qca8k_mdio_write(struct qca8k_priv *priv
|
||||
|
||||
exit:
|
||||
/* even if the busy_wait timeouts try to clear the MASTER_EN */
|
||||
- qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
|
||||
+ qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
|
||||
|
||||
mutex_unlock(&bus->mdio_lock);
|
||||
|
||||
@@ -814,18 +814,18 @@ qca8k_mdio_read(struct qca8k_priv *priv,
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
- qca8k_mii_write32(bus, 0x10 | r2, r1, val);
|
||||
+ qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val);
|
||||
|
||||
ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
|
||||
QCA8K_MDIO_MASTER_BUSY);
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
- ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
|
||||
+ ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val);
|
||||
|
||||
exit:
|
||||
/* even if the busy_wait timeouts try to clear the MASTER_EN */
|
||||
- qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
|
||||
+ qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0);
|
||||
|
||||
mutex_unlock(&bus->mdio_lock);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user