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https://github.com/openwrt/openwrt.git
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mediatek: backport latest pci/e driver from upstream
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
parent
5a5031e70b
commit
eff87b8f93
@ -257,18 +257,16 @@
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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status = "okay";
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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};
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pcie@0,0 {
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status = "okay";
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};
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pcie@1,0 {
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status = "okay";
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};
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&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_pins>;
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status = "okay";
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};
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&pio {
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@ -165,19 +165,14 @@
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};
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};
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&pcie {
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pinctrl-names = "default", "pcie1_pins";
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pinctrl-0 = <&pcie0_pins>;
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pinctrl-1 = <&pcie1_pins>;
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status = "okay";
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pcie@0,0 {
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status = "okay";
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mt7615@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x05000>;
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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mt7615@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&factory 0x05000>;
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};
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};
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&pio {
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@ -0,0 +1,646 @@
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "mt7622.dtsi"
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#include "mt6380.dtsi"
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/ {
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model = "MT7622_MT7531 RFB";
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compatible = "mediatek,mt7622,ubi";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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cpu@1 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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factory {
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label = "factory";
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linux,code = <BTN_0>;
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gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
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};
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};
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gsw: gsw@0 {
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compatible = "mediatek,mt753x";
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mediatek,ethsys = <ðsys>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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leds {
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compatible = "gpio-leds";
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green {
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label = "bpi-r64:pio:green";
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gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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red {
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label = "bpi-r64:pio:red";
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gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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memory {
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reg = <0 0x40000000 0 0x40000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&bch {
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status = "okay";
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};
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&btif {
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status = "okay";
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};
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&cir {
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pinctrl-names = "default";
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pinctrl-0 = <&irrx_pins>;
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&gsw {
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mediatek,mdio = <&mdio>;
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mediatek,portmap = "llllw";
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mediatek,mdio_master_pinmux = <0>;
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reset-gpios = <&pio 54 0>;
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interrupt-parent = <&pio>;
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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port5: port@5 {
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compatible = "mediatek,mt753x-port";
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reg = <5>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port6: port@6 {
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compatible = "mediatek,mt753x-port";
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reg = <6>;
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phy-mode = "sgmii";
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&emmc_pins_default>;
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pinctrl-1 = <&emmc_pins_uhs>;
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status = "okay";
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bus-width = <8>;
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max-frequency = <50000000>;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
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non-removable;
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};
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&mmc1 {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&sd0_pins_default>;
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pinctrl-1 = <&sd0_pins_uhs>;
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status = "okay";
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bus-width = <4>;
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max-frequency = <50000000>;
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cap-sd-highspeed;
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r_smpl = <1>;
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cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
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};
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&nandc {
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pinctrl-names = "default";
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pinctrl-0 = <¶llel_nand_pins>;
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status = "disabled";
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};
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&nor_flash {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_nor_pins>;
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status = "disabled";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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};
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&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_pins>;
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status = "okay";
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};
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&pio {
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/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
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* SATA functions. i.e. output-high: PCIe, output-low: SATA
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*/
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asm_sel {
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gpio-hog;
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gpios = <90 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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/* eMMC is shared pin with parallel NAND */
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emmc_pins_default: emmc-pins-default {
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mux {
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function = "emmc", "emmc_rst";
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groups = "emmc";
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};
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/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
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* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
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* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
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*/
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conf-cmd-dat {
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pins = "NDL0", "NDL1", "NDL2",
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"NDL3", "NDL4", "NDL5",
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"NDL6", "NDL7", "NRB";
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input-enable;
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bias-pull-up;
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};
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conf-clk {
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pins = "NCLE";
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bias-pull-down;
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};
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};
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emmc_pins_uhs: emmc-pins-uhs {
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mux {
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function = "emmc";
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groups = "emmc";
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};
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conf-cmd-dat {
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pins = "NDL0", "NDL1", "NDL2",
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"NDL3", "NDL4", "NDL5",
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"NDL6", "NDL7", "NRB";
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input-enable;
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drive-strength = <4>;
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bias-pull-up;
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};
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conf-clk {
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pins = "NCLE";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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eth_pins: eth-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio", "rgmii_via_gmac2";
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};
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};
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i2c1_pins: i2c1-pins {
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mux {
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function = "i2c";
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groups = "i2c1_0";
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};
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};
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i2c2_pins: i2c2-pins {
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mux {
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function = "i2c";
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groups = "i2c2_0";
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};
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};
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i2s1_pins: i2s1-pins {
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mux {
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function = "i2s";
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groups = "i2s_out_mclk_bclk_ws",
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"i2s1_in_data",
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"i2s1_out_data";
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};
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conf {
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pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
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"I2S_WS", "I2S_MCLK";
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drive-strength = <12>;
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bias-pull-down;
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};
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};
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irrx_pins: irrx-pins {
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mux {
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function = "ir";
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groups = "ir_1_rx";
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};
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};
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irtx_pins: irtx-pins {
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mux {
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function = "ir";
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groups = "ir_1_tx";
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};
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};
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/* Parallel nand is shared pin with eMMC */
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parallel_nand_pins: parallel-nand-pins {
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mux {
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function = "flash";
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groups = "par_nand";
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};
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};
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie0_pad_perst",
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"pcie0_1_waken",
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"pcie0_1_clkreq";
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};
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};
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pcie1_pins: pcie1-pins {
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mux {
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function = "pcie";
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groups = "pcie1_pad_perst",
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"pcie1_0_waken",
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"pcie1_0_clkreq";
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};
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};
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pmic_bus_pins: pmic-bus-pins {
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mux {
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function = "pmic";
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groups = "pmic_bus";
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};
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};
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pwm7_pins: pwm1-2-pins {
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mux {
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function = "pwm";
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groups = "pwm_ch7_2";
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};
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};
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wled_pins: wled-pins {
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mux {
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function = "led";
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groups = "wled";
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};
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};
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sd0_pins_default: sd0-pins-default {
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mux {
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function = "sd";
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groups = "sd_0";
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};
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/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
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* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
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* DAT2, DAT3, CMD, CLK for SD respectively.
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*/
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conf-cmd-data {
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pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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"I2S2_IN","I2S4_OUT";
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input-enable;
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drive-strength = <8>;
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bias-pull-up;
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};
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conf-clk {
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pins = "I2S3_OUT";
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drive-strength = <12>;
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bias-pull-down;
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};
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conf-cd {
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pins = "TXD3";
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bias-pull-up;
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};
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};
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sd0_pins_uhs: sd0-pins-uhs {
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mux {
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function = "sd";
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groups = "sd_0";
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};
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conf-cmd-data {
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pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
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"I2S2_IN","I2S4_OUT";
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input-enable;
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bias-pull-up;
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};
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conf-clk {
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pins = "I2S3_OUT";
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bias-pull-down;
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};
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};
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/* Serial NAND is shared pin with SPI-NOR */
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serial_nand_pins: serial-nand-pins {
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mux {
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function = "flash";
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groups = "snfi";
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};
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};
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spic0_pins: spic0-pins {
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mux {
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function = "spi";
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groups = "spic0_0";
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};
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};
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spic1_pins: spic1-pins {
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mux {
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function = "spi";
|
||||
groups = "spic1_0";
|
||||
};
|
||||
};
|
||||
|
||||
/* SPI-NOR is shared pin with serial NAND */
|
||||
spi_nor_pins: spi-nor-pins {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "spi_nor";
|
||||
};
|
||||
};
|
||||
|
||||
/* serial NAND is shared pin with SPI-NOR */
|
||||
serial_nand_pins: serial-nand-pins {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "snfi";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart0_0_tx_rx" ;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart2_1_tx_rx" ;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog_pins: watchdog-pins {
|
||||
mux {
|
||||
function = "watchdog";
|
||||
groups = "watchdog";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm7_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwrap {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_bus_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
&snfi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&serial_nand_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi_nand@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-nand";
|
||||
spi-max-frequency = <104000000>;
|
||||
reg = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Preloader";
|
||||
reg = <0x00000 0x0080000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ATF";
|
||||
reg = <0x80000 0x0040000>;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "Bootloader";
|
||||
reg = <0xc0000 0x0080000>;
|
||||
};
|
||||
|
||||
partition@140000 {
|
||||
label = "Config";
|
||||
reg = <0x140000 0x0080000>;
|
||||
};
|
||||
|
||||
factory: partition@1c0000 {
|
||||
label = "Factory";
|
||||
reg = <0x1c0000 0x0040000>;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x400000>;
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
label = "ubi";
|
||||
reg = <0x600000 0x1C00000>;
|
||||
};
|
||||
|
||||
partition@2200000 {
|
||||
label = "User_data";
|
||||
reg = <0x2200000 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spic0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spic1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
vusb33-supply = <®_3p3v>;
|
||||
vbus-supply = <®_5v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u3phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&watchdog_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wmac {
|
||||
mediatek,mtd-eeprom = <&factory 0x0000>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,420 @@
|
||||
From patchwork Thu May 28 06:16:45 2020
|
||||
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|
||||
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|
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|
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|
||||
X-Patchwork-Id: 11574793
|
||||
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From: <chuanjia.liu@mediatek.com>
|
||||
To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
|
||||
Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding
|
||||
Date: Thu, 28 May 2020 14:16:45 +0800
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Message-ID: <20200528061648.32078-2-chuanjia.liu@mediatek.com>
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Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
|
||||
srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
|
||||
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
|
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|
||||
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linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
|
||||
|
||||
From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
|
||||
|
||||
There are two independent PCIe controllers in MT2712/MT7622 platform,
|
||||
and each of them should contain an independent MSI domain.
|
||||
|
||||
In current architecture, MSI domain will be inherited from the root
|
||||
bridge, and all of the devices will share the same MSI domain.
|
||||
Hence that, the PCIe devices will not work properly if the irq number
|
||||
which required is more than 32.
|
||||
|
||||
Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
|
||||
comply with the hardware design.
|
||||
|
||||
Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
|
||||
---
|
||||
.../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++
|
||||
.../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
|
||||
2 files changed, 129 insertions(+), 53 deletions(-)
|
||||
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
|
||||
new file mode 100644
|
||||
index 000000000000..4d2835ab4858
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
|
||||
@@ -0,0 +1,38 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: Mediatek PCIECFG controller
|
||||
+
|
||||
+maintainers:
|
||||
+ - Chuanjia Liu <chuanjia.liu@mediatek.com>
|
||||
+ - Jianjun Wang <jianjun.wang@mediatek.com>
|
||||
+
|
||||
+description: |
|
||||
+ The MediaTek PCIECFG controller controls some feature about
|
||||
+ LTSSM, ASPM and so on.
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ items:
|
||||
+ - enum:
|
||||
+ - mediatek,mt7622-pciecfg
|
||||
+ - mediatek,mt7629-pciecfg
|
||||
+ - const: syscon
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ pciecfg: pciecfg@1a140000 {
|
||||
+ compatible = "mediatek,mt7622-pciecfg", "syscon";
|
||||
+ reg = <0 0x1a140000 0 0x1000>;
|
||||
+ };
|
||||
+...
|
||||
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
|
||||
index 7468d666763a..ddae110d4379 100644
|
||||
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
|
||||
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
|
||||
@@ -8,7 +8,7 @@ Required properties:
|
||||
"mediatek,mt7623-pcie"
|
||||
"mediatek,mt7629-pcie"
|
||||
- device_type: Must be "pci"
|
||||
-- reg: Base addresses and lengths of the PCIe subsys and root ports.
|
||||
+- reg: Base addresses and lengths of the root ports.
|
||||
- reg-names: Names of the above areas to use during resource lookup.
|
||||
- #address-cells: Address representation for root ports (must be 3)
|
||||
- #size-cells: Size representation for root ports (must be 2)
|
||||
@@ -19,10 +19,10 @@ Required properties:
|
||||
- sys_ckN :transaction layer and data link layer clock
|
||||
Required entries for MT2701/MT7623:
|
||||
- free_ck :for reference clock of PCIe subsys
|
||||
- Required entries for MT2712/MT7622:
|
||||
+ Required entries for MT2712/MT7622/MT7629:
|
||||
- ahb_ckN :AHB slave interface operating clock for CSR access and RC
|
||||
initiated MMIO access
|
||||
- Required entries for MT7622:
|
||||
+ Required entries for MT7622/MT7629:
|
||||
- axi_ckN :application layer MMIO channel operating clock
|
||||
- aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
|
||||
pcie_mac_ck/pcie_pipe_ck is turned off
|
||||
@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701:
|
||||
- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
|
||||
number of root ports.
|
||||
|
||||
-Required properties for MT2712/MT7622:
|
||||
+Required properties for MT2712/MT7622/MT7629:
|
||||
-interrupts: A list of interrupt outputs of the controller, must have one
|
||||
entry for each PCIe port
|
||||
|
||||
+Required properties for MT7622/MT7629:
|
||||
+- mediatek,pcie-subsys: Should be a phandle of the pciecfg node.
|
||||
+
|
||||
In addition, the device tree node must have sub-nodes describing each
|
||||
PCIe port interface, having the following mandatory properties:
|
||||
|
||||
@@ -143,56 +146,73 @@ Examples for MT7623:
|
||||
|
||||
Examples for MT2712:
|
||||
|
||||
- pcie: pcie@11700000 {
|
||||
+ pcie1: pcie@112ff000 {
|
||||
compatible = "mediatek,mt2712-pcie";
|
||||
device_type = "pci";
|
||||
- reg = <0 0x11700000 0 0x1000>,
|
||||
- <0 0x112ff000 0 0x1000>;
|
||||
- reg-names = "port0", "port1";
|
||||
+ reg = <0 0x112ff000 0 0x1000>;
|
||||
+ reg-names = "port1";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
|
||||
- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
|
||||
- <&pericfg CLK_PERI_PCIE0>,
|
||||
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
|
||||
<&pericfg CLK_PERI_PCIE1>;
|
||||
- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
|
||||
- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
|
||||
- phy-names = "pcie-phy0", "pcie-phy1";
|
||||
+ clock-names = "sys_ck1", "ahb_ck1";
|
||||
+ phys = <&u3port1 PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy1";
|
||||
bus-range = <0x00 0xff>;
|
||||
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
|
||||
+ status = "disabled";
|
||||
|
||||
- pcie0: pcie@0,0 {
|
||||
- reg = <0x0000 0 0 0 0>;
|
||||
+ slot1: pcie@1,0 {
|
||||
+ reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
- <0 0 0 2 &pcie_intc0 1>,
|
||||
- <0 0 0 3 &pcie_intc0 2>,
|
||||
- <0 0 0 4 &pcie_intc0 3>;
|
||||
- pcie_intc0: interrupt-controller {
|
||||
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
+ <0 0 0 2 &pcie_intc1 1>,
|
||||
+ <0 0 0 3 &pcie_intc1 2>,
|
||||
+ <0 0 0 4 &pcie_intc1 3>;
|
||||
+ pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
+ };
|
||||
|
||||
- pcie1: pcie@1,0 {
|
||||
- reg = <0x0800 0 0 0 0>;
|
||||
+ pcie0: pcie@11700000 {
|
||||
+ compatible = "mediatek,mt2712-pcie";
|
||||
+ device_type = "pci";
|
||||
+ reg = <0 0x11700000 0 0x1000>;
|
||||
+ reg-names = "port0";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
|
||||
+ <&pericfg CLK_PERI_PCIE0>;
|
||||
+ clock-names = "sys_ck0", "ahb_ck0";
|
||||
+ phys = <&u3port0 PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy0";
|
||||
+ bus-range = <0x00 0xff>;
|
||||
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ slot0: pcie@0,0 {
|
||||
+ reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
- <0 0 0 2 &pcie_intc1 1>,
|
||||
- <0 0 0 3 &pcie_intc1 2>,
|
||||
- <0 0 0 4 &pcie_intc1 3>;
|
||||
- pcie_intc1: interrupt-controller {
|
||||
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
+ <0 0 0 2 &pcie_intc0 1>,
|
||||
+ <0 0 0 3 &pcie_intc0 2>,
|
||||
+ <0 0 0 4 &pcie_intc0 3>;
|
||||
+ pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
@@ -202,39 +222,31 @@ Examples for MT2712:
|
||||
|
||||
Examples for MT7622:
|
||||
|
||||
- pcie: pcie@1a140000 {
|
||||
+ pcie0: pcie@1a143000 {
|
||||
compatible = "mediatek,mt7622-pcie";
|
||||
device_type = "pci";
|
||||
- reg = <0 0x1a140000 0 0x1000>,
|
||||
- <0 0x1a143000 0 0x1000>,
|
||||
- <0 0x1a145000 0 0x1000>;
|
||||
- reg-names = "subsys", "port0", "port1";
|
||||
+ reg = <0 0x1a143000 0 0x1000>;
|
||||
+ reg-names = "port0";
|
||||
+ mediatek,pcie-cfg = <&pciecfg>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
|
||||
- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AUX_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AXI_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P0_OBFF_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
- <&pciesys CLK_PCIE_P0_PIPE_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
|
||||
- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
|
||||
- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
|
||||
- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
|
||||
- phy-names = "pcie-phy0", "pcie-phy1";
|
||||
+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
|
||||
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
|
||||
+ "axi_ck0", "obff_ck0", "pipe_ck0";
|
||||
+
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
+ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x8000000>;
|
||||
+ status = "disabled";
|
||||
|
||||
- pcie0: pcie@0,0 {
|
||||
+ slot0: pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
@@ -251,8 +263,34 @@ Examples for MT7622:
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pcie@1a145000 {
|
||||
+ compatible = "mediatek,mt7622-pcie";
|
||||
+ device_type = "pci";
|
||||
+ reg = <0 0x1a145000 0 0x1000>;
|
||||
+ reg-names = "port1";
|
||||
+ mediatek,pcie-cfg = <&pciecfg>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
+ /* designer has connect RC1 with p0_ahb clock */
|
||||
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
|
||||
+ "axi_ck1", "obff_ck1", "pipe_ck1";
|
||||
+
|
||||
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
+ bus-range = <0x00 0xff>;
|
||||
+ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>;
|
||||
+ status = "disabled";
|
||||
|
||||
- pcie1: pcie@1,0 {
|
||||
+ slot1: pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
@ -0,0 +1,219 @@
|
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Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base
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|
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linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk
|
||||
Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
|
||||
Errors-To:
|
||||
linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
|
||||
|
||||
From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
|
||||
|
||||
Use regmap to get shared pcie-cfg base and change
|
||||
the method to get pcie irq.
|
||||
|
||||
Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
|
||||
---
|
||||
drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++-------
|
||||
1 file changed, 18 insertions(+), 7 deletions(-)
|
||||
|
||||
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
|
||||
index cb982891b22b..2268d6073eb6 100644
|
||||
--- a/drivers/pci/controller/pcie-mediatek.c
|
||||
+++ b/drivers/pci/controller/pcie-mediatek.c
|
||||
@@ -14,6 +14,7 @@
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/kernel.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
#include <linux/msi.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
@@ -23,6 +24,7 @@
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
+#include <linux/regmap.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
#include "../pci.h"
|
||||
@@ -205,6 +207,7 @@ struct mtk_pcie_port {
|
||||
* struct mtk_pcie - PCIe host information
|
||||
* @dev: pointer to PCIe device
|
||||
* @base: IO mapped register base
|
||||
+ * @cfg: IO mapped register map for PCIe config
|
||||
* @free_ck: free-run reference clock
|
||||
* @mem: non-prefetchable memory resource
|
||||
* @ports: pointer to PCIe port information
|
||||
@@ -214,6 +217,7 @@ struct mtk_pcie_port {
|
||||
struct mtk_pcie {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
+ struct regmap *cfg;
|
||||
struct clk *free_ck;
|
||||
|
||||
struct list_head ports;
|
||||
@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
|
||||
return err;
|
||||
}
|
||||
|
||||
- port->irq = platform_get_irq(pdev, port->slot);
|
||||
+ port->irq = platform_get_irq_byname(pdev, "pcie_irq");
|
||||
irq_set_chained_handler_and_data(port->irq,
|
||||
mtk_pcie_intr_handler, port);
|
||||
|
||||
@@ -673,12 +677,11 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
|
||||
if (!mem)
|
||||
return -EINVAL;
|
||||
|
||||
- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
|
||||
- if (pcie->base) {
|
||||
- val = readl(pcie->base + PCIE_SYS_CFG_V2);
|
||||
- val |= PCIE_CSR_LTSSM_EN(port->slot) |
|
||||
- PCIE_CSR_ASPM_L1_EN(port->slot);
|
||||
- writel(val, pcie->base + PCIE_SYS_CFG_V2);
|
||||
+ /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */
|
||||
+ if (pcie->cfg) {
|
||||
+ val = PCIE_CSR_LTSSM_EN(port->slot) |
|
||||
+ PCIE_CSR_ASPM_L1_EN(port->slot);
|
||||
+ regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
|
||||
}
|
||||
|
||||
/* Assert all reset signals */
|
||||
@@ -984,6 +987,7 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
|
||||
struct device *dev = pcie->dev;
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
struct resource *regs;
|
||||
+ struct device_node *cfg_node;
|
||||
int err;
|
||||
|
||||
/* get shared registers, which are optional */
|
||||
@@ -996,6 +1000,13 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
|
||||
}
|
||||
}
|
||||
|
||||
+ cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0);
|
||||
+ if (cfg_node) {
|
||||
+ pcie->cfg = syscon_node_to_regmap(cfg_node);
|
||||
+ if (IS_ERR(pcie->cfg))
|
||||
+ return PTR_ERR(pcie->cfg);
|
||||
+ }
|
||||
+
|
||||
pcie->free_ck = devm_clk_get(dev, "free_ck");
|
||||
if (IS_ERR(pcie->free_ck)) {
|
||||
if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
|
||||
@ -0,0 +1,423 @@
|
||||
From patchwork Thu May 28 06:16:47 2020
|
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|
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X-Patchwork-Id: 11574785
|
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From: <chuanjia.liu@mediatek.com>
|
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To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
|
||||
Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for
|
||||
MT2712/MT7622
|
||||
Date: Thu, 28 May 2020 14:16:47 +0800
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|
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Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
|
||||
srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
|
||||
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
|
||||
yong.wu@mediatek.com, bhelgaas@google.com,
|
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linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk
|
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|
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Errors-To:
|
||||
linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
|
||||
|
||||
From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
|
||||
|
||||
There are two independent PCIe controllers in MT2712/MT7622 platform,
|
||||
and each of them should contain an independent MSI domain.
|
||||
|
||||
In current architecture, MSI domain will be inherited from the root
|
||||
bridge, and all of the devices will share the same MSI domain.
|
||||
Hence that, the PCIe devices will not work properly if the irq number
|
||||
which required is more than 32.
|
||||
|
||||
Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
|
||||
comply with the hardware design.
|
||||
|
||||
Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
|
||||
---
|
||||
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++++++++--------
|
||||
.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 ++--
|
||||
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +-
|
||||
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 +++++++++++------
|
||||
4 files changed, 96 insertions(+), 69 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
|
||||
index 2cd8b33886e5..ab27ff4a869e 100644
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
|
||||
@@ -797,60 +797,73 @@
|
||||
};
|
||||
};
|
||||
|
||||
- pcie: pcie@11700000 {
|
||||
+ pcie1: pcie@112ff000 {
|
||||
compatible = "mediatek,mt2712-pcie";
|
||||
device_type = "pci";
|
||||
- reg = <0 0x11700000 0 0x1000>,
|
||||
- <0 0x112ff000 0 0x1000>;
|
||||
- reg-names = "port0", "port1";
|
||||
+ reg = <0 0x112ff000 0 0x1000>;
|
||||
+ reg-names = "port1";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
|
||||
- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
|
||||
- <&pericfg CLK_PERI_PCIE0>,
|
||||
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
|
||||
<&pericfg CLK_PERI_PCIE1>;
|
||||
- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
|
||||
- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
|
||||
- phy-names = "pcie-phy0", "pcie-phy1";
|
||||
+ clock-names = "sys_ck1", "ahb_ck1";
|
||||
+ phys = <&u3port1 PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy1";
|
||||
bus-range = <0x00 0xff>;
|
||||
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
|
||||
+ status = "disabled";
|
||||
|
||||
- pcie0: pcie@0,0 {
|
||||
- device_type = "pci";
|
||||
- status = "disabled";
|
||||
- reg = <0x0000 0 0 0 0>;
|
||||
+ slot1: pcie@1,0 {
|
||||
+ reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
- <0 0 0 2 &pcie_intc0 1>,
|
||||
- <0 0 0 3 &pcie_intc0 2>,
|
||||
- <0 0 0 4 &pcie_intc0 3>;
|
||||
- pcie_intc0: interrupt-controller {
|
||||
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
+ <0 0 0 2 &pcie_intc1 1>,
|
||||
+ <0 0 0 3 &pcie_intc1 2>,
|
||||
+ <0 0 0 4 &pcie_intc1 3>;
|
||||
+ pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
+ };
|
||||
|
||||
- pcie1: pcie@1,0 {
|
||||
- device_type = "pci";
|
||||
- status = "disabled";
|
||||
- reg = <0x0800 0 0 0 0>;
|
||||
+ pcie0: pcie@11700000 {
|
||||
+ compatible = "mediatek,mt2712-pcie";
|
||||
+ device_type = "pci";
|
||||
+ reg = <0 0x11700000 0 0x1000>;
|
||||
+ reg-names = "port0";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
|
||||
+ <&pericfg CLK_PERI_PCIE0>;
|
||||
+ clock-names = "sys_ck0", "ahb_ck0";
|
||||
+ phys = <&u3port0 PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy0";
|
||||
+ bus-range = <0x00 0xff>;
|
||||
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ slot0: pcie@0,0 {
|
||||
+ reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
- <0 0 0 2 &pcie_intc1 1>,
|
||||
- <0 0 0 3 &pcie_intc1 2>,
|
||||
- <0 0 0 4 &pcie_intc1 3>;
|
||||
- pcie_intc1: interrupt-controller {
|
||||
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
+ <0 0 0 2 &pcie_intc0 1>,
|
||||
+ <0 0 0 3 &pcie_intc0 2>,
|
||||
+ <0 0 0 4 &pcie_intc0 3>;
|
||||
+ pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
index 83e10591e0e5..7574d88cc46a 100644
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
@@ -207,18 +207,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
-&pcie {
|
||||
+&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
|
||||
+ pinctrl-0 = <&pcie0_pins>;
|
||||
status = "okay";
|
||||
+};
|
||||
|
||||
- pcie@0,0 {
|
||||
- status = "okay";
|
||||
- };
|
||||
-
|
||||
- pcie@1,0 {
|
||||
- status = "okay";
|
||||
- };
|
||||
+&pcie1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
index 339dc9f88f43..d5131c8b6a79 100644
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -766,45 +766,41 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
- pcie: pcie@1a140000 {
|
||||
+ pciecfg: pciecfg@1a140000 {
|
||||
+ compatible = "mediatek,mt7622-pciecfg", "syscon";
|
||||
+ reg = <0 0x1a140000 0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ pcie0: pcie@1a143000 {
|
||||
compatible = "mediatek,mt7622-pcie";
|
||||
device_type = "pci";
|
||||
- reg = <0 0x1a140000 0 0x1000>,
|
||||
- <0 0x1a143000 0 0x1000>,
|
||||
- <0 0x1a145000 0 0x1000>;
|
||||
- reg-names = "subsys", "port0", "port1";
|
||||
+ reg = <0 0x1a143000 0 0x1000>;
|
||||
+ reg-names = "port0";
|
||||
+ mediatek,pcie-cfg = <&pciecfg>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
|
||||
- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
- <&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AUX_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AXI_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P0_OBFF_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
- <&pciesys CLK_PCIE_P0_PIPE_EN>,
|
||||
- <&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
|
||||
- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
|
||||
- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
|
||||
+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
|
||||
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
|
||||
+ "axi_ck0", "obff_ck0", "pipe_ck0";
|
||||
+
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
|
||||
status = "disabled";
|
||||
|
||||
- pcie0: pcie@0,0 {
|
||||
+ slot0: pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
- status = "disabled";
|
||||
-
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
@@ -816,15 +812,39 @@
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
+ };
|
||||
|
||||
- pcie1: pcie@1,0 {
|
||||
+ pcie1: pcie@1a145000 {
|
||||
+ compatible = "mediatek,mt7622-pcie";
|
||||
+ device_type = "pci";
|
||||
+ reg = <0 0x1a145000 0 0x1000>;
|
||||
+ reg-names = "port1";
|
||||
+ mediatek,pcie-cfg = <&pciecfg>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
+ /* designer has connect RC1 with p0_ahb clock */
|
||||
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
|
||||
+ "axi_ck1", "obff_ck1", "pipe_ck1";
|
||||
+
|
||||
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
+ bus-range = <0x00 0xff>;
|
||||
+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ slot1: pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
- status = "disabled";
|
||||
-
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:25.092948824 +0800
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts 2020-06-15 18:52:15.909094229 +0800
|
||||
@@ -244,18 +244,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
-&pcie {
|
||||
+&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
|
||||
+ pinctrl-0 = <&pcie0_pins>;
|
||||
status = "okay";
|
||||
+};
|
||||
|
||||
- pcie@0,0 {
|
||||
- status = "okay";
|
||||
- };
|
||||
-
|
||||
- pcie@1,0 {
|
||||
- status = "okay";
|
||||
- };
|
||||
+&pcie1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
@ -0,0 +1,207 @@
|
||||
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Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
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|
||||
Remove unused property and add pciecfg node.
|
||||
|
||||
Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
|
||||
---
|
||||
arch/arm/boot/dts/mt7629-rfb.dts | 3 ++-
|
||||
arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++----------
|
||||
2 files changed, 15 insertions(+), 11 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/mt7629-rfb.dts b/arch/arm/boot/dts/mt7629-rfb.dts
|
||||
index 9980c10c6e29..eb536cbebd9b 100644
|
||||
--- a/arch/arm/boot/dts/mt7629-rfb.dts
|
||||
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
|
||||
@@ -140,9 +140,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
-&pcie {
|
||||
+&pcie1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
+ status = "okay";
|
||||
};
|
||||
|
||||
&pciephy1 {
|
||||
diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
|
||||
index 5cbb3d244c75..94567307b842 100644
|
||||
--- a/arch/arm/boot/dts/mt7629.dtsi
|
||||
+++ b/arch/arm/boot/dts/mt7629.dtsi
|
||||
@@ -360,16 +360,21 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
- pcie: pcie@1a140000 {
|
||||
+ pciecfg: pciecfg@1a140000 {
|
||||
+ compatible = "mediatek,mt7629-pciecfg", "syscon";
|
||||
+ reg = <0x1a140000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pcie@1a145000 {
|
||||
compatible = "mediatek,mt7629-pcie";
|
||||
device_type = "pci";
|
||||
- reg = <0x1a140000 0x1000>,
|
||||
- <0x1a145000 0x1000>;
|
||||
- reg-names = "subsys","port1";
|
||||
+ reg = <0x1a145000 0x1000>;
|
||||
+ reg-names = "port1";
|
||||
+ mediatek,pcie-cfg = <&pciecfg>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
|
||||
- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupt-names = "pcie_irq";
|
||||
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
@@ -390,21 +395,19 @@
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
|
||||
+ status = "disabled";
|
||||
|
||||
- pcie1: pcie@1,0 {
|
||||
- device_type = "pci";
|
||||
+ slot1: pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
- num-lanes = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
-
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
Loading…
Reference in New Issue
Block a user