mirror of
https://github.com/openwrt/openwrt.git
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ipq806x: Initial TP-Link and ASUS OnHub support
TP-Link and ASUS OnHub devices are very similar, sharing many of the same characteristics and much of their Device Tree. They both run a version of ChromeOS for their factory firmware, and so installation instructions look very similar to Google Wifi [1]. Things I've tested, and are working: * Ethernet * WiFi (2.4 and 5 GHz) * LEDs * USB * eMMC * Serial console (if you wire it up yourself) * 2x CPU * Speaker == Installation instructions summary == 1. Flash *-factory.bin to a USB drive (e.g., with `dd`) 2. Insert USB drive, to boot OpenWrt from USB 3. Copy the same *-factory.bin over to device, and flash it to eMMC to make OpenWrt permanent == Developer mode, booting from USB (Step 2) == To enter Developer Mode and boot OpenWrt from a USB stick: 1. Unplug power 2. Gain access to the "developer switch" through the bottom of the device 3. Hold down the "reset switch" (near the USB port / power plug) 4. Plug power back in 5. The LED on the device should turn white, then blink orange, then red. Release the reset switch. 6. Insert USB drive with OpenWrt factory.bin 7. Press the hidden developer switch under the device to boot to USB; you should see some activity lights (if you have any) on your USB drive 8. Depending on your configuration, the router's LED(s) should come on. You're now running OpenWrt off a USB stick. These instructions are derived from: https://www.exploitee.rs/index.php/Rooting_The_Google_OnHub#Enabling_%22Developer_Mode%22_on_the_OnHub https://www.exploitee.rs/index.php/Asus_OnHub#Enabling_%22Developer_Mode%22_on_the_OnHub ~~Finding the developer switch:~~ for TP-Link, the developer switch is on the bottom of the device, underneath some of the rubber padding and a screw. For ASUS, remove the entire base, via 4 screws under the rubber feet. See the Exploitee instructions for more info and photos. == Making OpenWrt permanent (on eMMC) (Step 3) == Once you're running OpenWrt via USB: 1. Connect Ethernet to the LAN port; router's LAN address should be at 192.168.1.1 2. Connect another system to the router's LAN, and copy the factory.bin image over, via SCP and SSH: scp -O openwrt-ipq806x-chromium-tplink_onhub-squashfs-factory.bin root@192.168.1.1: ssh root@192.168.1.1 -C "dd if=/dev/zero bs=512 seek=7552991 of=/dev/mmcblk0 count=33 && \ dd if=/root/openwrt-ipq806x-chromium-tplink_onhub-squashfs-factory.bin of=/dev/mmcblk0" 3. Reboot and remove the USB drive. == Developer mode beep == Note that every time you boot the OnHub in developer mode, the device will play a loud "beep" after a few seconds. This is described in the Chromium docs [2], and is intended to make it clear that the device is not running Google software. It is nontrivial to completely disable this beep, although it's possible to "acknowledge" developer mode (and skip the beep) by using a USB keyboard to press CTRL+D every time you boot. [1] https://openwrt.org/toh/google/wifi [2] https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Brian Norris
Christian Marangi
parent
bd0f9d8ffc
commit
ef649b0b14
@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk
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ARCH:=arm
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BOARD:=ipq806x
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BOARDNAME:=Qualcomm Atheros IPQ806X
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FEATURES:=squashfs nand fpu ramdisk
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FEATURES:=squashfs fpu ramdisk
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CPU_TYPE:=cortex-a15
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CPU_SUBTYPE:=neon-vfpv4
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SUBTARGETS:=generic
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SUBTARGETS:=generic chromium
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KERNEL_PATCHVER:=5.15
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@ -79,6 +79,12 @@ tplink,ad7200)
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ucidef_add_switch "switch0" \
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"2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0"
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;;
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asus,onhub |\
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tplink,onhub)
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ucidef_set_interfaces_lan_wan "eth1" "eth0"
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ucidef_add_switch "switch0" \
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"1:lan" "6@eth1" "2:wan" "0@eth0"
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;;
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ubnt,unifi-ac-hd)
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ucidef_set_interface_lan "eth0 eth1"
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;;
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@ -6,9 +6,32 @@
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board=$(board_name)
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dt_base64_extract() {
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local target_dir="/sys$DEVPATH"
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local source="$target_dir/../../of_node/qcom,ath10k-calibration-data-base64"
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[ -e "$source" ] || caldata_die "cannot find base64 calibration data: $source"
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[ -d "$target_dir" ] || \
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caldata_die "no sysfs dir to write: $target"
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echo 1 > "$target_dir/loading"
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base64decode.uc "$source" > "$target_dir/data"
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if [ $? != 0 ]; then
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echo 1 > "$target_dir/loading"
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caldata_die \
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"failed to write calibration data to $target_dir/data"
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else
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echo 0 > "$target_dir/loading"
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fi
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}
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case "$FIRMWARE" in
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"ath10k/cal-pci-0000:01:00.0.bin")
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case "$board" in
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asus,onhub |\
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tplink,onhub)
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dt_base64_extract
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;;
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meraki,mr52)
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CI_UBIPART=art
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caldata_extract_ubi "ART" 0x1000 0x844
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@ -35,6 +58,14 @@ case "$FIRMWARE" in
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;;
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esac
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;;
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"ath10k/cal-pci-0001:01:00.0.bin")
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case "$board" in
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asus,onhub |\
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tplink,onhub)
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dt_base64_extract
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;;
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esac
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;;
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"ath10k/pre-cal-pci-0001:01:00.0.bin")
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case $board in
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asrock,g10)
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@ -61,6 +92,10 @@ case "$FIRMWARE" in
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;;
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"ath10k/cal-pci-0002:01:00.0.bin")
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case "$board" in
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asus,onhub |\
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tplink,onhub)
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dt_base64_extract
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;;
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meraki,mr42)
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CI_UBIPART=art
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caldata_extract_ubi "ART" 0x9000 0x844
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@ -57,6 +57,15 @@ platform_do_upgrade() {
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MTD_CONFIG_ARGS="-s 0x200000"
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default_do_upgrade "$1"
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;;
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asus,onhub |\
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tplink,onhub)
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export_bootdevice
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export_partdevice CI_ROOTDEV 0
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CI_KERNPART="kernel"
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CI_ROOTPART="rootfs"
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CI_DATAPART="rootfs_data"
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emmc_do_upgrade "$1"
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;;
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tplink,vr2600v)
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MTD_CONFIG_ARGS="-s 0x200000"
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default_do_upgrade "$1"
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@ -69,3 +78,13 @@ platform_do_upgrade() {
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;;
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esac
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}
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platform_copy_config() {
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case "${board_name}" in
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asus,onhub |\
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tplink,onhub)
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emmc_copy_config
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;;
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esac
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return 0
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}
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23
target/linux/ipq806x/base-files/usr/bin/base64decode.uc
Executable file
23
target/linux/ipq806x/base-files/usr/bin/base64decode.uc
Executable file
@ -0,0 +1,23 @@
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#!/usr/bin/ucode
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import { stdin, open, error } from 'fs';
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if (length(ARGV) == 0 && stdin.isatty()) {
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warn("usage: b64decode [stdin|path]\n");
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exit(1);
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}
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let fp = stdin;
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let source = ARGV[0];
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if (source) {
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fp = open(source);
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if (!fp) {
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warn('b64decode: unable to open ${source}: ${error()}\n');
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exit(1);
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}
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}
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print(b64dec(fp.read("all")));
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fp.close();
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exit(0);
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13
target/linux/ipq806x/chromium/config-default
Normal file
13
target/linux/ipq806x/chromium/config-default
Normal file
@ -0,0 +1,13 @@
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CONFIG_BLK_DEV_SD=y
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CONFIG_LEDS_LP5523=y
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CONFIG_LEDS_LP55XX_COMMON=y
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CONFIG_PHY_QCOM_IPQ806X_USB=y
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CONFIG_SCSI=y
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CONFIG_SCSI_COMMON=y
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CONFIG_SG_POOL=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_HOST=y
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CONFIG_USB_DWC3_QCOM=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PLATFORM=y
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2
target/linux/ipq806x/chromium/target.mk
Normal file
2
target/linux/ipq806x/chromium/target.mk
Normal file
@ -0,0 +1,2 @@
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BOARDNAME:=Google Chromium
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FEATURES += emmc boot-part rootfs-part
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@ -0,0 +1,96 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2014 The ChromiumOS Authors
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*/
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#include "qcom-ipq8064-onhub.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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model = "ASUS OnHub";
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compatible = "asus,onhub", "google,arkham", "qcom,ipq8064";
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chosen {
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bootargs-append = " rootwait";
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};
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};
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&qcom_pinmux {
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ap3223_pins: ap3223_pinmux {
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pins = "gpio22";
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function = "gpio";
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bias-none;
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};
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i2c7_pins: i2c7_pinmux {
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mux {
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pins = "gpio8", "gpio9";
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function = "gsbi7";
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};
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data {
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pins = "gpio8";
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bias-disable;
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};
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clk {
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pins = "gpio9";
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bias-disable;
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};
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};
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};
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&gsbi7 {
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status = "okay";
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qcom,mode = <GSBI_PROT_I2C_UART>;
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};
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&gsbi7_i2c {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c7_pins>;
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pinctrl-names = "default";
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ap3223@1c {
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compatible = "dynaimage,ap3223";
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reg = <0x1c>;
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pinctrl-0 = <&ap3223_pins>;
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pinctrl-names = "default";
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int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
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};
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led-controller@32 {
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compatible = "national,lp5523";
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reg = <0x32>;
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clock-mode = /bits/ 8 <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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led@4 {
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reg = <4>;
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color = <LED_COLOR_ID_GREEN>;
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chan-name = "green:status";
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linux,default-trigger = "default-on";
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led-cur = /bits/ 8 <0xfa>;
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max-cur = /bits/ 8 <0xff>;
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};
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led@5 {
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reg = <5>;
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color = <LED_COLOR_ID_BLUE>;
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chan-name = "blue:status";
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led-cur = /bits/ 8 <0xfa>;
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max-cur = /bits/ 8 <0xff>;
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};
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led@8 {
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reg = <8>;
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color = <LED_COLOR_ID_RED>;
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chan-name = "red:status";
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led-cur = /bits/ 8 <0xfa>;
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max-cur = /bits/ 8 <0xff>;
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};
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};
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};
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@ -0,0 +1,463 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2014 The ChromiumOS Authors
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*/
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#include "qcom-ipq8064-smb208.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/soc/qcom,tcsr.h>
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/ {
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac2;
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mdio-gpio0 = &mdio;
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serial0 = &gsbi4_serial;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rsvd@41200000 {
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reg = <0x41200000 0x300000>;
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no-map;
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};
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};
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mdio: mdio {
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compatible = "virtual,mdio-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
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<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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phy0: ethernet-phy@0 {
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reg = <0>;
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qca,ar8327-initvals = <
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0x00004 0x7600000 /* PAD0_MODE */
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0x00008 0x1000000 /* PAD5_MODE */
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0x0000c 0x80 /* PAD6_MODE */
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0x000e4 0xaa545 /* MAC_POWER_SEL */
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0x000e0 0xc74164de /* SGMII_CTRL */
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0x0007c 0x4e /* PORT0_STATUS */
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0x00094 0x4e /* PORT6_STATUS */
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>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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soc {
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rng@1a500000 {
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status = "disabled";
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};
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sound {
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compatible = "google,storm-audio";
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qcom,model = "ipq806x-storm";
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cpu = <&lpass>;
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codec = <&max98357a>;
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};
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lpass: lpass@28100000 {
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status = "okay";
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pinctrl-names = "default", "idle";
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pinctrl-0 = <&mi2s_default>;
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pinctrl-1 = <&mi2s_idle>;
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};
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max98357a: max98357a {
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compatible = "maxim,max98357a";
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#sound-dai-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmode_pins>;
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sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&qcom_pinmux {
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rgmii0_pins: rgmii0_pins {
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mux {
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pins = "gpio2", "gpio66";
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drive-strength = <8>;
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bias-disable;
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};
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};
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mi2s_pins {
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mi2s_default: mi2s_default {
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dout {
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pins = "gpio32";
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function = "mi2s";
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drive-strength = <16>;
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bias-disable;
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};
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sync {
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pins = "gpio27";
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function = "mi2s";
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drive-strength = <16>;
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bias-disable;
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};
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clk {
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pins = "gpio28";
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function = "mi2s";
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drive-strength = <16>;
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bias-disable;
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};
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};
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mi2s_idle: mi2s_idle {
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dout {
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pins = "gpio32";
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function = "mi2s";
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drive-strength = <2>;
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bias-pull-down;
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};
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sync {
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pins = "gpio27";
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function = "mi2s";
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drive-strength = <2>;
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bias-pull-down;
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};
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clk {
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pins = "gpio28";
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function = "mi2s";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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mdio_pins: mdio_pins {
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mux {
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pins = "gpio0", "gpio1";
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function = "gpio";
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drive-strength = <8>;
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bias-disable;
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};
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rst {
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pins = "gpio26";
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output-low;
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};
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};
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sdmode_pins: sdmode_pinmux {
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pins = "gpio25";
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function = "gpio";
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drive-strength = <16>;
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bias-disable;
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};
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sdcc1_pins: sdcc1_pinmux {
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mux {
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pins = "gpio38", "gpio39", "gpio40",
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"gpio41", "gpio42", "gpio43",
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"gpio44", "gpio45", "gpio46",
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"gpio47";
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function = "sdc1";
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};
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cmd {
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pins = "gpio45";
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drive-strength = <10>;
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bias-pull-up;
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};
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data {
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pins = "gpio38", "gpio39", "gpio40",
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"gpio41", "gpio43", "gpio44",
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"gpio46", "gpio47";
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drive-strength = <10>;
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bias-pull-up;
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};
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clk {
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pins = "gpio42";
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drive-strength = <16>;
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bias-pull-down;
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};
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};
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i2c1_pins: i2c1_pinmux {
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pins = "gpio53", "gpio54";
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function = "gsbi1";
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bias-disable;
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};
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rpm_i2c_pinmux: rpm_i2c_pinmux {
|
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mux {
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pins = "gpio12", "gpio13";
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function = "gsbi4";
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drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
bias-pull-down;
|
||||
/delete-property/ bias-none;
|
||||
/delete-property/ drive-strength;
|
||||
};
|
||||
data {
|
||||
pins = "gpio18", "gpio19";
|
||||
drive-strength = <10>;
|
||||
};
|
||||
cs {
|
||||
pins = "gpio20";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
clk {
|
||||
pins = "gpio21";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
fw_pinmux {
|
||||
wp {
|
||||
pins = "gpio17";
|
||||
output-low;
|
||||
};
|
||||
recovery {
|
||||
pins = "gpio16";
|
||||
bias-none;
|
||||
};
|
||||
developer {
|
||||
pins = "gpio15";
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
|
||||
spi6_pins: spi6_pins {
|
||||
mux {
|
||||
pins = "gpio55", "gpio56", "gpio58";
|
||||
function = "gsbi6";
|
||||
bias-pull-down;
|
||||
};
|
||||
data {
|
||||
pins = "gpio55", "gpio56";
|
||||
drive-strength = <10>;
|
||||
};
|
||||
cs {
|
||||
pins = "gpio57";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
clk {
|
||||
pins = "gpio58";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <0>;
|
||||
phy-handle = <&phy1>;
|
||||
|
||||
pinctrl-0 = <&rgmii0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac2 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi1 {
|
||||
status = "okay";
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
};
|
||||
|
||||
&gsbi1_i2c {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
tpm@20 {
|
||||
compatible = "infineon,slb9645tt";
|
||||
reg = <0x20>;
|
||||
powered-while-suspended;
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
status = "okay";
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
};
|
||||
|
||||
&gsbi4_serial {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gsbi5 {
|
||||
status = "okay";
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "okay";
|
||||
spi-max-frequency = <50000000>;
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 0>;
|
||||
|
||||
flash: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi6 {
|
||||
status = "okay";
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
};
|
||||
|
||||
&gsbi6_spi {
|
||||
status = "okay";
|
||||
spi-max-frequency = <25000000>;
|
||||
|
||||
pinctrl-0 = <&spi6_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
dmas = <&adm_dma 8 0xb>,
|
||||
<&adm_dma 7 0x14>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
/*
|
||||
* This "spidev" was included in the manufacturer device tree. I suspect
|
||||
* it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
|
||||
* no driver or binding for this at the moment.
|
||||
*/
|
||||
spidev@0 {
|
||||
compatible = "spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
|
||||
ath10k@0,0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
device_type = "pci";
|
||||
qcom,ath10k-sa-gpio = <2 3 4 0>;
|
||||
qcom,ath10k-sa-gpio-func = <5 5 5 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
|
||||
ath10k@0,0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
device_type = "pci";
|
||||
qcom,ath10k-sa-gpio = <2 3 4 0>;
|
||||
qcom,ath10k-sa-gpio-func = <5 5 5 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
|
||||
ath10k@0,0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rpm {
|
||||
pinctrl-0 = <&rpm_i2c_pinmux>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&sdcc1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&sdcc1_pins>;
|
||||
pinctrl-names = "default";
|
||||
/delete-property/ mmc-ddr-1_8v;
|
||||
};
|
||||
|
||||
&tcsr {
|
||||
compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
|
||||
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
|
||||
};
|
||||
|
||||
&hs_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ss_phy_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hs_phy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ss_phy_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -0,0 +1,213 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2014 The ChromiumOS Authors
|
||||
*/
|
||||
|
||||
#include "qcom-ipq8064-onhub.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
|
||||
/ {
|
||||
model = "TP-Link OnHub";
|
||||
compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064";
|
||||
|
||||
chosen {
|
||||
bootargs-append = " rootwait";
|
||||
};
|
||||
};
|
||||
|
||||
&qcom_pinmux {
|
||||
i2c7_pins: i2c7_pinmux {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9";
|
||||
function = "gsbi7";
|
||||
};
|
||||
data {
|
||||
pins = "gpio8";
|
||||
bias-disable;
|
||||
};
|
||||
clk {
|
||||
pins = "gpio9";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi7 {
|
||||
status = "okay";
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
};
|
||||
|
||||
&gsbi7_i2c {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&i2c7_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led-controller@32 {
|
||||
compatible = "national,lp5523";
|
||||
reg = <0x32>;
|
||||
clock-mode = /bits/ 8 <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
chan-name = "red:status-0";
|
||||
linux,default-trigger = "default-on";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
chan-name = "green:status-0";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
chan-name = "blue:status-0";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
chan-name = "red:status-1";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
chan-name = "green:status-1";
|
||||
linux,default-trigger = "default-on";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@5 {
|
||||
reg = <5>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
chan-name = "blue:status-1";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@6 {
|
||||
reg = <6>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
chan-name = "red:status-2";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@7 {
|
||||
reg = <7>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
chan-name = "green:status-2";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@8 {
|
||||
reg = <8>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
chan-name = "blue:status-2";
|
||||
linux,default-trigger = "default-on";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
};
|
||||
|
||||
led-controller@33 {
|
||||
compatible = "national,lp5523";
|
||||
reg = <0x33>;
|
||||
clock-mode = /bits/ 8 <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
chan-name = "red:status-3";
|
||||
linux,default-trigger = "default-on";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
chan-name = "green:status-3";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
chan-name = "blue:status-3";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
chan-name = "red:status-4";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
chan-name = "green:status-4";
|
||||
linux,default-trigger = "default-on";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@5 {
|
||||
reg = <5>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
chan-name = "blue:status-4";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@6 {
|
||||
reg = <6>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
chan-name = "red:status-5";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@7 {
|
||||
reg = <7>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
chan-name = "green:status-5";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
|
||||
led@8 {
|
||||
reg = <8>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
chan-name = "blue:status-5";
|
||||
linux,default-trigger = "default-on";
|
||||
led-cur = /bits/ 8 <0x64>;
|
||||
max-cur = /bits/ 8 <0x78>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1 +1,2 @@
|
||||
BOARDNAME:=Generic
|
||||
FEATURES += nand
|
||||
|
||||
58
target/linux/ipq806x/image/chromium.mk
Normal file
58
target/linux/ipq806x/image/chromium.mk
Normal file
@ -0,0 +1,58 @@
|
||||
define Build/cros-gpt
|
||||
cp $@ $@.tmp 2>/dev/null || true
|
||||
ptgen -o $@.tmp -g \
|
||||
-T cros_kernel -N kernel -p $(CONFIG_TARGET_KERNEL_PARTSIZE)m \
|
||||
-N rootfs -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)m \
|
||||
-N rootfs_data -p \
|
||||
$$((3687-$(CONFIG_TARGET_ROOTFS_PARTSIZE)-\
|
||||
$(CONFIG_TARGET_KERNEL_PARTSIZE)))m
|
||||
cat $@.tmp >> $@
|
||||
rm $@.tmp
|
||||
endef
|
||||
|
||||
define Build/append-kernel-part
|
||||
dd if=$(IMAGE_KERNEL) bs=$(CONFIG_TARGET_KERNEL_PARTSIZE)M conv=sync >> $@
|
||||
endef
|
||||
|
||||
# NB: Chrome OS bootloaders replace the '%U' in command lines with the UUID of
|
||||
# the kernel partition it chooses to boot from. This gives a flexible way to
|
||||
# consistently build and sign kernels that always use the subsequent
|
||||
# (PARTNROFF=1) partition as their rootfs.
|
||||
define Build/cros-vboot
|
||||
$(STAGING_DIR_HOST)/bin/cros-vbutil \
|
||||
-k $@ -c "root=PARTUUID=%U/PARTNROFF=1" -o $@.new
|
||||
@mv $@.new $@
|
||||
endef
|
||||
|
||||
define Device/OnhubImage
|
||||
KERNEL_LOADADDR = 0x44208000
|
||||
SOC := qcom-ipq8064
|
||||
KERNEL_SUFFIX := -fit-zImage.itb.vboot
|
||||
KERNEL_NAME := zImage
|
||||
KERNEL = kernel-bin | fit none $$(KDIR)/image-$$(DEVICE_DTS).dtb | cros-vboot
|
||||
IMAGES := factory.bin sysupgrade.bin
|
||||
IMAGE/factory.bin := cros-gpt | append-kernel-part | append-rootfs
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct e2fsprogs kmod-fs-ext4 losetup \
|
||||
partx-utils mkf2fs kmod-fs-f2fs \
|
||||
ucode kmod-google-firmware kmod-tpm-i2c-infineon \
|
||||
kmod-sound-soc-ipq8064-storm kmod-usb-storage
|
||||
endef
|
||||
|
||||
define Device/asus_onhub
|
||||
$(call Device/OnhubImage)
|
||||
DEVICE_VENDOR := ASUS
|
||||
DEVICE_MODEL := OnHub SRT-AC1900
|
||||
DEVICE_DTS := $$(SOC)-asus-onhub
|
||||
BOARD_NAME := asus-onhub
|
||||
endef
|
||||
TARGET_DEVICES += asus_onhub
|
||||
|
||||
define Device/tplink_onhub
|
||||
$(call Device/OnhubImage)
|
||||
DEVICE_VENDOR := TP-Link
|
||||
DEVICE_MODEL := OnHub AC1900 Cloud Router
|
||||
DEVICE_DTS := $$(SOC)-tplink-onhub
|
||||
BOARD_NAME := tplink-onhub
|
||||
endef
|
||||
TARGET_DEVICES += tplink_onhub
|
||||
Loading…
Reference in New Issue
Block a user